Multiple industries, including mobile consumer, industrial electronics and automotive electronics will benefit from the project, said consortium coordinator Infineon.
The ESiP (Efficient Silicon Multi-Chip Systems-in-Package Integration) project is intended to improve reliability and testability of highly integrated microelectronics systems. In order to achieve this goal, the consortium will develop production processes and explore new materials, an Infineon spokesperson said. Common denominator of the project partners is the estimate that the significance of the multi-chip system-in-package products for future applications will increase.
These products combine several integrated circuits produced in different technologies in one package either side by side or stacked above one another. Back-end processing and testing of such devices contains a number of challenges to manufacturers. For this reason, the project also will include the development of new methods of error analysis and testing.
The project brings 40 companies from nine European countries to the table. Infineon as the consortium leader announced to contribute its experience in producing 3D stacked semiconductors. Other participants include Siemens AG and a number of Fraunhofer research institutes.
The budget for the project amounts to 35 million (about $46 million), with half of that sum funded by the project partners. Of the remaining 50 percent, two thirds will be provided by national funding organizations in the participating countries – Austria, Belgium, Finland, France, Germany, Italy, Netherlands, Norway and the UK. The remainder is funded by the European Community.