One of the biggest challenges in analog/mixed-signal IC design is uncertainty in electrical behavior and reliability. While uncertainty can be a problem at any process node, it is particularly pronounced at the advanced nodes that will be needed to meet demands in high-growth areas like mobile computing. In conventional custom IC design flows, there is little observability into the electrical impact of physical design decisions until the layout is complete and design intent can be verified through parasitic extraction and circuit simulation. The combination of electrical uncertainty combined with increasing sensitivity of AMS designs to parasitics and layout dependent effects can result in significantly higher turn-around times and more conservative designs that sacrifice performance for reliability. To mitigate the risks associated with moving to advanced nodes, IC design teams will require EDA solutions that reduce electrical uncertainty and ensure design intent is preserved during custom design.
An ideal solution would electrically verify the performance and reliability of every single physical design decision so the layout is electrically correct by construction and optimized to meet the design intent. This article describes a new EDA methodology, called electrically-aware design, where every physical design decision regarding placement and routing can be analyzed or visualized in terms of its impact on electrical performance and reliability. While this methodology can be applied to a number of use models, this article focuses on reducing the uncertainty associated with electromigration (EM)-related reliability, an increasingly serious problem at advanced process nodes.
Design productivity and time to market are highly dependent on reducing uncertainties introduced during physical design. Uncertainty in the electrical behavior and reliability of analog/mixed-signal chips results from the sensitivity of analog devices to variability and the complex parasitic interactions among devices and interconnect. Additional uncertainty results from manufacturing and layout-dependent geometric dimensions, orientations, and the distances between adjacent devices. In addition, the ability to create identical devices is often critical to meeting electrical performance and design intent from a circuit perspective.
Design choices may be used to minimize variation and maximize performance, but understanding which choice is appropriate for a given context can be a complex undertaking. In conventional custom design methodologies, designers are forced to make physical design decisions with little or no way to immediately measure the electrical consequences of their decisions. Verification through simulation or reliability checking conventionally occurs when the physical design is complete, often requiring multiple design iterations to achieve successful silicon. The lack of electrical observability until the very end makes it harder to identify the cause of the unwanted behavior and reduces the set of potential fixes.
Electrically-aware design will provide designers and layout engineers with immediate electrical feedback as layout shapes are created, and it will do this in-design. This in-design verification will also allow the electrical intent of the designer to be fed forward to ensure that each step in physical design meets their desired electrical intent. New methodologies will be required to enable incremental extraction and electrical analysis, and to provide observability into the consequences of design decisions as each decision is made. Electrically-aware design improves productivity by reducing the number of design iterations and the overall uncertainty that leads to overly conservative designs and reduced in-silicon performance and profitability.
Electromigration and its causes
Electromigration (EM) effects can seriously damage interconnect wires and vias, having an adverse impact on IC reliability. Electrically-aware design provides new in-design methodology opportunities for EM verification, and the same general methodology could be applied to a range of in-design electrical checking and simulation solutions.
EM is the transport of material in a solid conductor that results from collisions between the flow of electrons and metal atoms in the interconnect. Proportional to the current per unit area, the continual movement of metal atoms from their lattice position can lead to a degradation in performance as the resistance of the interconnect increases. At some point the wire eventually fails, creating an electrical open (void) or short connection (hillock) downstream.
The dominant factor in determining mean time to failure (MTTF) is the current density. Since current density depends on the wire geometry, it cannot be determined until the routed net is generated. Given that the width of the wire or via is a variable, designers need to know whether the current flowing through that particular area has exceeded the maximum allowed current. The maximum current limit for a given geometry is expressed as rules that every wire segment or via must adhere to for a specified operating or maximum temperature. This set of rules is contained in a technology file that is computed and distributed according to each process technology specification.
With the aggressive scaling of interconnect geometries at advanced technology nodes, the EM effects are dependent not only on the local current density of a geometric wire segment or via, but also on the homogeneity of the current flow through a region. As such, current density limits or rules vary based on not just each geometric dimension of the wire segments and vias, but on the geometries of the connecting wires and vias as well.
There are additional complications. There is a minimum length below which the net won't fail due to EM, commonly referred to as Blech length. This adds another dimension to the problem of sizing a wire for EM. The EM rules for a metal layer are specified in buckets for different limits based on the width and length of shapes on the layer. Without assistance from an EDA tool, it would be cumbersome for a layout engineer to route nets on various layers and account for the ever-increasing number of EM rules associated with these buckets.
The EM rules become even more complicated when vias and contacts are considered. Traditionally, single via or contact cuts had a current density number associated with them, while clusters of vias would have more relaxed rules. At advanced technology nodes, a single via or contact will have different current density limits based on different shapes (e.g. square or rectangular). This issue is compounded when additional conductors are connected to the via(s) and the current density limits can change based on the width and length of the connecting conductors.
This behavior is illustrated in Figure 1 with three interconnect examples that are based on different widths and lengths of connecting wires. All three have different current density (EM) limits. Each has an upper and lower interconnect wire connected through the same via shape, but each example forms a different geometric profile where the length or width dimensions of the interconnect differ.
The leftmost connection in the figure has the shortest lengths in the dimension of the upper and lower interconnect wires, with the result that the connecting via cut has the highest current density limit and thus can carry the most current without violating the limit. The middle connection has the same interconnect wire width as the left one, but the wire lengths of the upper and lower interconnect are much longer. The impact is that the current density limit for the via cut is lower than the left example. As such, the middle connection can carry less current and remain within the EM-related reliability limits.
In the rightmost connection in Figure 1, the upper and lower interconnect lengths are the same but the width of the wires coming into the via are reduced. The result is that the current density limit for the via cut is significantly reduced from the middle and leftmost examples. Note that in all three examples the via geometry is the same and, if examined without any context of the surrounding wire geometry, it is impossible to know which current density limits to apply.
Figure 1: Geometric-based rules require proximity of current calculations with conductor (net) geometry
In addition to the geometric properties of the interconnect, the underlying topology of the routing can also significantly change the distribution of current flow and, subsequently, current densities. Thus the same geometric description (such as a specific width and length of a wire) may or may not meet pre-specified current density limits, depending on the topology of the surrounding interconnect.
Figures 2 and 3 highlight a case where the incoming current to the MOS device may be connected to the strap in two different locations. In Figure 2, the current is sourced into one side of the M2 strap, which results in a large amount of current flowing through the strap to reach the M1 vertical finger connections on the other end. Color coding is used to indicate the proximity of that wire location to the specified current density limit. In this case, the green coding indicates that the current is far from reaching the limit; red coding represents that the current is over the limit for that particular wire segment.
Figure 2: Connection to MOS device resulting in current density violations with highlighted circle noting the current density violations in finger connections to the source
In Figure 3, the incoming current is connected to the middle of the M2 strap and, as such, the current is distributed more evenly throughout the source vertical connections (fingers). As the color coding indicates, the current limit is not exceeded, even though the geometric properties of the fingers, strap, and incoming wire are very similar—the primary distinction being where the connection has been made. This example also illustrates why it is difficult to specify current-correct routing decisions a priori without knowledge of the underlying topology. This rather simple case was chosen to illustrate the problem, but there are many such cases where the correction to the routing topology is not straightforward, often resulting in a cycle of layout modification, extraction, and analysis.
Figure 3: Alternate connection to same MOS device from previous figure, resulting in no current density violations
The prior examples illustrate just some of the complexities of designing at advanced nodes. As the rules become more geometry-dependent, it will become increasingly difficult to know which wire segments or vias to fix and how to do so without creating another violation. The following paragraphs propose an electrically-aware design methodology for in-design EM checking that improves productivity while reducing the risk and uncertainty of moving to advanced nodes.
Electrically-aware, “in design” verification
As shown in Figure 4, the in-design flow begins with creation of a schematic that is simulated and modified to meet the designer’s specifications. After the ideal, pre-layout simulation is completed, the currents at each terminal are saved. A testbench setup is configured to generate the average, RMS, and peak currents necessary for EM checking.
Figure 4: In-design EM verification methodology allows for current densities to be computed and checked as interconnect is incrementally created or modified
After device creation and placement, routing is initiated. For a given interconnect geometry to be routed, the EM limits should verify that it is below the maximum current or current density allowed for each segment of the net. To solve the current flow, parasitics need to be extracted as the net is routed and sized. The extracted parasitics are then used to solve current distribution throughout the wires and vias that constitute a net, with extraction and current solving occurring as the net is created.
Foundries create and maintain EM-related current density limits to ensure reliability of the manufactured device over years of operation at nominal and elevated temperatures. These limits are provided in a technology file and, as discussed above, are growing increasingly complex with geometric dependencies. During layout creation, the limits from the techfile are loaded and made available for in-design verification. The current limits and the solved currents for each geometric shape or set of net shapes are checked as layout edits are made.
Use models for electrically-aware, in-design verification and optimization fall into three basic categories: manual, assisted, and automatic. It is likely that a manual use mode will be adopted by users first until they are confident that in-design solutions provide accurate problem detection and correction. The results can be displayed in real time as color-coded overlays on the layout (Figures 2 and 3), or a threshold may be set where only violations are shown.
When violations are identified in the GUI, the user can simply click on the net and resize the wire. Incremental electrical analysis immediately checks the edit, and when the wire is sufficiently wide, the display is updated accordingly (as indicated with the green overlay). Sometimes resizing may not be sufficient or desirable. In those cases, movement of the route location may be necessary, as shown in Figure 3. Once the net passes verification, the user can move to the next net to be routed.
In the assisted use mode, once a current density limit violation is identified, the tool will compute and display a suggested fix such as“increase wire width by 100%.” The user would have the option to review and approve fixes individually or simply approve all. As the user becomes more comfortable with the suggested modifications from the tools, in-design solutions can drive more automatic wire sizing and routing changes during the routing process. This approach is often referred to as current-driven routing, which may take the form of a feed-forward approach (a topology editor and wire size selection are used to select net properties prior to physical routing), or a feedback approach (an optimization loop and cost function are used to iterate after the net is routed until the acceptance criteria are met).
For analog/mixed-signal chips, the reduction of uncertainty during physical design will similarly reduce overly conservative design practices and improve return on investment in terms of in-silicon performance and profitability. Electrically-aware, in-design verification methodologies will reduce uncertainty through electrical assessment, verification, and optimization of each incremental physical design decision. One of the largest contributors to electrical uncertainty is the current density limits imposed by electromigration, and most believe these limits will become even more complex at 20nm and beyond.
In this article, new methodologies have been proposed to incrementally extract parasitic and check current-related limits as each net is routed. Initial solutions will likely identify solutions and provide users with assistance in resolving any problems. As users become more confident in the ability of in-design solutions to automatically correct such issues, the introduction of current-driven routing methodologies and solutions will be addressed. These solutions will evolve toward the ultimate goal, which is an EDA solution that generates layout that is electrically correct by construction and minimizes turnaround time for analog/mixed-signal designs.
Electrically-aware design is discussed in more detail in the recently published Cadence® Mixed-Signal Methodology Guide .
 Mixed-Signal Methodology Guide: Advanced Methodology for AMS IP and SoC Design, Verification, and Implementation, J. Chen, et. al, eds., Cadence Design Systems, 2012.
About the authors
David White received a Doctor of Science Degree in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology in 2001. He currently directs R&D for Virtuoso Electrically Aware Design products at Cadence Design Systems in San Jose, California. He joined Cadence in 2006 through the acquisition of Praesagus, a software company he co-founded in 2001 and where he served as Chief Technology Officer until the merger. Dr. White has served as a member of the Advisory Board for the National Science Foundation (NSF) in Washington D.C. as well as advisory boards at MIT and early stage companies.
Akshat Shah received his Bachelors of Science Degree in Electrical and Computer Engineering from Carnegie Mellon University and his Masters in Business Administration from the University of Pittsburgh. Akshat is currently the Product Engineering Director for Virtuoso platform. His team is responsible for the Virtuoso Front-End, the Electrically Aware Design flow and the 20nm Advanced Nodes Flow. He joined Cadence thru the Neolinear acquisition in 2006 where he was a Product Engineer and drove the NeoCircuit and NeoCell products which are now part of the Virtuoso platform.
Article Courtesy: EE Times