Real Intent Inc., a provider of software products that accelerate Early Functional Verification and Advanced Sign-Off of electronic designs, announced it is now shipping version 1.5 of its Ascent Lint software.
Ascent Lint adds over 40 new rules for Verilog, VHDL and SystemVerilog designs, covering both RTL and gate-level netlists. These checks help catch bugs and improve design quality early in the design cycle.
Ascent Lint claims to improve usability with enhancements to the lint debugger GUI and lint policy configuration utility, a more robust waiving capability, and better lint documentation. These features offer greater ease-of-use and faster turnaround for designers.
The product detects complex design bugs early in the design flow, finds design and coding guiding bottlenecks that impact simulation, synthesis, testability, and implementation costs, offers easy adoption, use and customization, integrates with Real Intent’s tools and plugs straight into standard EDA flows and helps geographically dispersed design teams to create higher quality designs.
The company claimed the software has the highest performance of any lint tool in the industry, is low-noise, yet comprehensive violations report, has fast debugging capability with cross probing to RTL design source and pinpoints the exact source of issues, offers rules from STARC Verilog and VHDL Policy, Verilog and System Veri-log Gotchas, Reuse Methodology Manual, Principles of Verifiable RTL Designs, DataPath Synthesis rules, and rules based on Real Intent industry expertise, and, provides GUI for rule selection, waiving, and customization as well as debugging the violations report.