Digital routing for 28 nanometer

by Alexander Volkov, Mentor Graphics , TechOnline India - December 23, 2011

To meet quality, time-to-market, and cost targets for 28-nm and below, designers must adopt new routing technologies that can solve for multiple design objectives within the scope of required tool capacity, memory footprint, and runtime.

With the adoption of each new process node comes new challenges that require new techniques and tools to solve. With 28-nm, a primary hurdle is with digital routing. Physical design tools must now manage complex design rule checking (DRC) and design for manufacturing (DFM) rules, increasing rule counts, very large (1 billion  transistor) designs, and multiple optimization objectives. Using a router that worked for the previous node might not be feasible. To meet quality, time-to-market, and cost targets for 28-nm and below, designers must adopt new routing technologies that can solve for multiple design objectives within the scope of required tool capacity, memory footprint, and runtime.


Nanometer Routing Challenges

The main challenges at 28-nm that require new routing technologies include:
   • Increasing number and complexity of DRC/DFM rules
   • Need for accurate and early estimations of routing resources
   • Inefficient physical signoff and engineering change order (ECO) iterations
Increasing DRC/DFM Requirements

When trying to print features smaller than the wavelength of light used in the lithography process, inevitably parametric, systematic, and random manufacturing defects occur. Design rules and DFM requirements exist to correct for these sub-wavelength effects. Between the 90-nm and 28-nm nodes, integrated device manufacturers (IDMs) and foundries have roughly doubled the number of design rules required to ensure layout features known to affect yield are not introduced into the design (Figure 1). In addition, model-based DFM analysis is also being used to detect more subtle yield limiters, and is becoming mandatory. All of these factors make designers more responsible for ensuring that a design not only meets functional and performance specifications, but is also manufacturable.


Figure 1. Foundries require more design rules with each process node to ensure manufacturability. The increased number and complexity of design rules poses a challenge to digital signal routers.

For 28-nm, foundries provide “recommended rules” in addition to the mandatory DRC rules. Recommended rules are soft rules designed to improve the yield, and each comes with a priority that reflects its relative impact on manufacturability. Although the recommended rules are discretionary, if they are not honored during implementation the yield may not be optimal.

Inaccurate Global Routing Estimation

All routers use a similar multi-step process that involves creating estimates the available routing resources before adding the final, detailed routes. The accuracy of this first ‘global routing’ step is very important in terms of design time and quality of the results (QoR). Some routing engines use only a subset of the foundry design rules in a simplified form for global routing, and invoke the full set of DRC rules only for detail routing. They end up simply counting the number of routing tracks across the chip that meet minimum spacing requirements. The result is poor correlation between early estimates and final routing results and ultimately, routing closure problems.

The estimate must take into account complex resource requirements such as the effect of vias and stacked via arrays, blockages, and staggered macros. It must also consider design rule compliance and SI requirements like wire spreading, wire widening, and shielding.
Inefficient Physical Signoff and ECOs

The traditional decoupling of the routing and the signoff verification engines poses another key challenge at 28-nm. A router typically uses simplified DRC and DFM models as part of the trade-off between runtime and accuracy during routing. Once the implementation is complete, the GDSII layout is verified using signoff-quality DRC/DFM models and Standard Verification Rule Format (SVRF) rule decks. For previous nodes, this flow worked well enough because the number of violations discovered at signoff was relatively low. But at advanced nodes, there can be a huge number of DRC/DFM violations, and ECOs fixes can lead to new violations and also degrade performance and power targets of the design.

There is a also growing difference between the rules using during design and those in the signoff rule deck. As a new process node matures, the foundry’s design rule files (expressed in the SVRF language used by sign-off engines) are constantly updated to address manufacturing issues as they are discovered. Consequently, these foundry signoff models are always the most accurate and complete representation of actual manufacturing requirements. The rules used by the place and route system, expressed in LEF or similar syntax, are simpler and can fall out of sync with the foundry rules. Further, some rules for 28-nm are too complex to be expressed in the simpler LEF language. As a result, the router will report the layout to be DRC/DFM, but signoff analysis finds a large number of violations.

Designers are also finding that DFM techniques, including metal fill/CMP, litho, and critical area analysis, are starting to affect the traditional design metrics like timing, power, and signal integrity. There has been no automated way to repair the DRC/DFM violations, and no way to ensure that DFM enhancements don’t degrade other design metrics. The traditional flow requires the transfer of huge ASCII files between the implementation and signoff environments, which further slows the design process. In summary, the design-then-verify flow that has worked in the past is increasingly unmanageable and unpredictable.


Can Your Router Handle 28-nm?

Your router for 28-nm IC designs needs to be flexible and robust. It should support both gridded and non-gridded models and use a universal connectivity model for a friendly ECO flow. It must also support sophisticated non-default rules (NDRs) and all the DFM requirements for advanced nodes including recommended rules, redundant vias, wire spreading and widening, and timing-aware metal and via fill. Finally, because of the large size of many 28-nm ICs and SoCs, the router needs to use multiple cores and CPUs and physical memory very efficiently. The requirements of a routing system for 28-nm are illustrated in Figure 2.

Figure 2. A convergent digital IC routing flow for advanced-node designs.


Comprehensive 28 nm DRC / DFM Rules Support

The routing engine must comply with all the complex design rules as defined by the foundries at 28-nm. It should have mechanisms to address the increased number and complexity of DRC rules, for example through intelligently minimizing the number of operation performed during routing, thereby minimizing the impact on runtime. It should use the full DRC/DFM models during all stages of routing, which gives better accuracy and fewer violations during post-route optimization and signoff. The DRC engine should check for violations based on polygon shapes rather than edge-to-edge checks, which enables complex 28-nm rules to be represented and adhered to effectively.

In addition to the default hard rules, the router should also support recommended, or soft, rules and the corresponding rule priorities. Automatic routing repair should be performed based on the priority as defined by the foundry or by the user.
Accurate Estimation in Global Routing 

A timing- and congestion-aware 3D global router is essential for getting the most accurate routing layer resources estimations. The global router should also use the complete set of DRC/DFM rules, including recommended rules, to avoid intractable DFM problems that show up as late-stage surprises. If a router cannot accurately measure the resources used by vias or stacked via patterns, it will make inaccurate congestion estimates. Be sure your router uses new modeling technologies that account for the resources consumed by vias or stacked via patterns.
Routing for Variability, Timing and SI

Variability must be accounted for at all levels of design at 28-nm. To ensure optimization of all design parameters across all process and operational modes and corners, the router should be multi-mode, multi-corner (MCMM) aware. 

Traditional routers use static SI models and proxy models, instead of native analysis, which can be slower and less accurate than what designers need. Newer routers do better by having SI costing native to the routing kernel, which allows for dynamic, incremental, MCMM SI analysis. Using incremental, on-the-fly extraction, polygon-based DRC analysis, and MCMM timing analysis lets a router make quick decisions on issues such as increased spacing, wire spreading, and rerouting for critical nets.


Signoff DRC and DFM Integrated with the Router

Advanced IC designs require a fundamental change in the physical design flow so that physical signoff can be directly invoked from the place and route environment. This integrated flow requires a new flexible architecture so that the router can natively perform SVRF-based DRC and DFM analysis. This flow ensures that all manufacturability issues are addressed without introducing new ones, and without degrading the performance of the design. It also significantly speeds up the manufacturing signoff process, and delivers higher quality results with faster time to market.

Enabling access to the actual signoff engines running golden SVRF rule decks is the key to the effectiveness of an integrated design/signoff tool. Using proven Calibre signoff technologies means that there are no new rule languages, tools, or methodologies to learn. Designers will save time and disk space because there are no large ASCII files to transfer between tools. Other features of the integrated design/signoff tool improve productivity, like on-demand GDSII abstraction, which allow designers to find LVS and DRC problems that are caused by mismatches between GDSII and abstract views.

High Capacity and Fast Turn-Around-Time

A router for 28-nm must have an extremely efficient and scalable data model to address the growing design sizes. When assessing performance, consider that the number of operations the router must perform at 28-nm is nearly four times more than what was required at the 65-nm node. Several techniques can be used to maintain the routing runtime for these big designs. One is a method for clustering and filtering rules. Rather than applying each rule separately, the tool can detect rule commonalities and group them for more efficient processing. 

Another important performance factor is the efficient use multiple CPUs. Figure 3 illustrates the speedup that can be achieved for different CPU configurations when the place and route tool architecture has a very efficient data model and is built for maximum parallelism. 


Figure 3. Routing speedup with Multi-CPU runs using the Mentor Graphics’ Olympus-SoC place and route system.


IC designs at 28-nm face a host of significant routing challenges due to the increased number and complexity of DRC/DFM requirements, increased design sizes, and multiple design goals. Routers for 28-nm must offer a flexible and powerful architecture to address these concerns and achieve optimal QoR across all design metrics in the shortest time.


About the author:

Alexander Volkov is Principal Technologist, Place & Route, MentorGraphics



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