Analysis: Intel slowly gears up for system-on-chips

TechOnline India - July 09, 2009

Intel Corp. isn't giving much detail on its two-year old initiative to become a systems-on-chip supplier, but interviews with executives and analysts show the company is making gradual progress laying the foundations to build competitive SoCs for cellphones, TVs, videogame consoles and communications gear.

SAN JOSE, Calif. — Intel Corp. isn't giving much detail on its two-year old initiative to become a systems-on-chip supplier. But interviews with executives and analysts show the company is making gradual progress laying the foundations to build competitive SoCs for cellphones, TVs, videogame consoles and communications gear.

The initiative strategically opens up whole new markets for Intel beyond its maturing PC business. But it requires new tools and skills for the company, and it puts Intel into direct competition with ARM Ltd., IBM Corp., MIPS Technologies and the long list of well-established embedded chip makers using those company's cores.

The x86 giant's first crop of SoCs so far has failed to gain any design wins among top tier OEMs. Nevertheless, Intel has made strides developing the process technology, design tools, interconnect strategy and silicon blocks it needs to become a significant player.

In a series of interviews, Intel execs sketched out the company's progress to date. They were most specific in the area of the company's greatest strength—process technology.

Intel has completed work on a low power version of its 45nm process geared for making SoCs and it will have a 32nm version available for its chip designers to use next year. Going forward, the company plans to develop separate versions of its process technology for high performance PC processors and low power SoCs, including 22nm versions already in the works.

In addition to the high performance transistors used for PC processors, the SoC process also offers transistors that have 10 to 1,000 times less power leakage. However, the thicker oxide layers on those circuits reduce their performance by a factor of three.

"That's a pretty good trade off," said Mark Bohr, an Intel senior fellow of logic technology development.

Intel's senior fellow of logic technology development
Mark Bohr

The SoC process also supports a wider range of high voltage I/Os, up to 3.3V, to interface with older silicon blocks and NAND memory. In addition, it includes a library of high precision inductors, resistors, capacitors and varactors used in RF and other analog blocks.

"This suite of features is typically available in other SoC processes from other companies," said Bohr. "What makes us unique is we can do it with high-k metal gate transistors to get down to really low leakage," factors that help support low power and high voltage operations, he added.

Metal finger capacitors (left) and inductors (right).

In addition, SoC designers can also use the high performance transistors geared for PC processors. The SoC process "gives us an excellent combination of performance with low active and leakage power, said Gadi Singer, a veteran Intel exec driving the corporate SoC initiative quietly launched in mid-2007.

Creating the low power version of the process requires "a very small incremental cost," Bohr said.

Intel has 14 SoCs now in development that will use its 32nm low power process (called P1269) now being tested. The 45nm SoC process (P1266.8) has a subset of its features, and it is being used for products in pilot production now, including integrated mobile and TV processors called Lincroft and Sodaville, respectively.

Singer said the 32nm SoCs will use a common framework. It includes the new process technology, a "fabric" of Intel-defined on-chip interconnects, a new EDA flow with an SoC test methodology and a shared library of silicon blocks.

{pagebreak}Perhaps the least public and most intriguing part of Intel's SoC initiative involves the deal it announced with Taiwan Semiconductor Manufacturing Co. in March. The two companies said they are porting to a standard TSMC process Intel's low power Atom chip—the x86 core that will be at the heart of all its future SoCs.

The objective is to let companies design their own ASICs using the Atom core and TSMC's process technology, EDA tool flow and library of silicon blocks. But the rules of the road for such engagements, exactly what process they are targeting or the current status of the Atom port are all unclear.

Bohr said he believed the Atom port would be available in a TSMC 40-45nm process.

An Intel spokeswoman sketched out the business dynamics:

"The customer relationship belongs to Intel," she said. "If a customer decides on the Atom core they then will work with Intel to meet their requirements. If they want to use TSMC because of previous relationships or capabilities then Intel will work with the customer to make that happen. The financial terms are confidential."

TSMC declined to elaborate on the deal. "We are pretty much muzzled," a TSMC spokeswoman said.

Interestingly, neither Bohr nor Intel chief technology officer Justin Rattner could respond to analyst Tom Halfhill, senior editor of the Microprocessor Report, when he asked whether the deal means Intel is licensing Atom.

"They didn't really know the answer. They were confused and I was confused," said Halfhill.

Despite the murky details, the objective seems clear, said Linley Gwennap, principal of market watcher The Linley Group (Mountain View, Calif.). Intel wants to win away from IBM and others the lucrative and secretive business of making custom processors for next-generation videogame consoles and set-top boxes and other systems, he said.

Today, IBM makes ASICs for all three top consoles—the Microsoft Xbox 360, Nintendo Wii and Sony Playstation. Set-top box giants such as Cisco System's Scientific Atlanta group create proprietary processors using cores such as the Sun Microsystems Sparc along with SA's own silicon blocks.

"There are really only a few companies in the world that want to do this" kind of ASIC design, said Gwennap. "If Intel wants to get into next-generation Xbox, they have to have an offering like this," he added.

Indeed, one unconfirmed report has already emerged about Sony using for its next-gen Playstation a version of Intel's upcoming Larrabee graphics processor. The chip uses an array of x86 cores in a manner roughly similar to the multicore IBM Cell, a proprietary variant of which is in today's Playstation.

The TSMC deal also marks Intel's first step toward building an ecosystem of partners around Atom-based SoCs. In this area, the PC giant is years behind archrival ARM which has a long list of well established licensees using its cores, especially for cellphone handsets, the big kahuna of new markets for Intel.

ARM's licensees get access to soft cores they can use in any way in their designs as long as they remain compatible with a defined instruction set. A handful of licensees such as Marvell and Qualcomm have architectural licenses with ARM, letting them create custom instruction sets with unique features or performance advantages.

One of Intel's highest profile customers, Apple Inc., appears to be emerging as one of Intel's competitors in SoCs for mobile devices.

"I believe Apple does have an ARM architectural license and is designing its own custom ARM cores for future iPhones and iPods," said Halfhill. "I think they brought the PA Semi team in to do custom ARM designs, but that's just my speculation," he added.

Unlike ARM, Intel has no synthesizeable version of its x86 core, preferring the performance of a fixed core defined in hardware to the flexibility of a software-based one. Ceva Inc. offers a similar service at TSMC with its hard DSP core.

Thus Intel's customers likely will be confined to using a hardware-defined core. "It's a more restrictive model at best," said Halfhill, "and my understanding is Intel controls the design."

{pagebreak}Intel has made significant progress defining an EDA tool flow for its SOCs, mainly using third party software programs. But in line with its longstanding policy, it is not divulging whose EDA tools it uses.

"We have selected from EDA industry tools and some internal tools," said Singer, a former head of chip-design software for Intel. "We are not in the final stage, but we are in an advanced stage of convergence--in less than a year everything will be done in a converged flow," he said.

"Part of flow deals with the integration of components into SoCs with a lot of emphasis on post-silicon and moving to a volume ramp, external tests and test access points," Singer added.

General manager of Intel's system-on-chip enabling group
Gadi Singer

Testing and validating silicon blocks is one of the thorniest issues in SoC design with multiple chip and software companies offering competing products. Singer said he wants to see standards emerge.

"This is where I would really encourage IP, EDA and integration houses to work together to reduce complexity and cost," he said.

The situation is different in the key on-chip interconnects used to link silicon blocks on an SoC. Intel has developed its own so-called "fabric" of interconnect standards for internal use only and it has no plans of making the details public.

An Intel spokeswoman describes the fabric as "a hierarchical on-chip interconnect with protocols, verification environment, [design-for-test and -manufacturing] capabilities and [a] compliance test suite. In addition it contains Intel specific features both for backward compatibility as well as to support PC requirements," she said.

Singer said the fabric has interconnects that support Windows device enumeration for legacy PC applications. It can also accommodate " industry buses and sockets," he said, declining to provide specifics.

"The way it works is we identify the IP important to our products, and then find out they are on industry standard buses and make sure that's not a barrier," said Singer. "We are not endorsing or supporting any standards," he said.

Presumably, Intel does not want to promote the widely used on-chip interconnects developed by ARM, its archrival in mobile systems. However, venture capitalists have called for Intel to reveal what on-chip interconnects it uses so that their startups can plan to plug into them.

"I don't know why they are being so cagey about it, but at some point it doesn't matter depending on what they are willing to do to make things happen," said Gwennap of The Linley Group. "It's interesting to me that they are willing to use third-party IP which is something they haven't done much of in the past," he said.

{pagebreak}Intel says it has "dozens of IP blocks ready or in development for [it's undisclosed] SoC fabric." The company has used a relatively small number of generally PC-centric blocks so far.

Intel's Tolapai SoCs released in July 2008 for communications systems mainly consisted of Pentium M cores and their associated memory and I/O controllers—essentially a PC on a chip. The Canmore SoC for digital TVs that debuted in August 2008 included a number of blocks from Intel's PC chip set group such as cores for 2.5 GHz PCI Express, serial ATA 2.0, USB 2.0 and Gigabit Ethernet.

Intel designed three other blocks for Canmore. They included an MPEG2/H.264 decode block based on technology acquired from Israeli startup O-Plus, a display processor for scaling and interlacing and a security processor. Canmore also sported a graphics block from Imagination Technologies, a company Intel and Apple have both used and invested in.

Intel lacks the wealth of consumer or communications blocks available in the ASIC processes of companies such as Panasonic or LSI Corp. To cover more bases, especially in comms, Intel has developed a generic accelerator it calls Quick Assist and published an applications programming interface for it so customers can create their own blocks for comms functions not in Intel's IP library.

"Our strategy is If we can run a function on a multicore x86, we will do that first," said Rose Schooler, general manager for SoCs in Intel's embedded group. "In some cases we offer the accelerator, and that's why an open API is so critical for us," she said.

To help fill the gaps in mobile, Intel struck a partnership with Nokia in late June, licensing its 3G silicon blocks. Such baseband capabilities are increasingly used in handset application processors from competitors such as Qualcomm, said Gwennap of The Linley Group.

"If Intel doesn't have that capability, they won't get anywhere," said Gwennap. "It's definitely something they need to be serious about smart phones," he said.

But Intel is playing catch up. ST Ericsson is already sampling its U8500 cellphone processor. It combines two ARM Cortex A9 cores with a Nokia baseband block.

Nokia has announced it will buy handset SoCs from ST Ericsson, Broadcom and Qualcomm for future smart phones. Thus Intel needs Nokia more than Nokia needs Intel.

Meanwhile other companies are working on single-and dual-core ARM chips that hit data rates of a GHz or more. They will attack Intel's premise of having a more powerful mobile processor than its competitors.

{pagebreak}Intel has yet to gain a major OEM design win for its SoCs, despite the release last July of multiple Tolapai SoCs for a variety of communications systems and the high-profile August launch of Canmore for digital TVs.

That's left analysts underwhelmed at Intel's SoC initiative to date.

"It's still too early to tell where they are going with this, but after all the noise last year I'm surprised there hasn't been more follow up," said Gwennap of The Linley Group. "They keep telling us they were working on 32nm SoCs and stuff using the Atom core which would be more efficient, but they haven't announced anything," he said.

Rivals such as Qualcomm and Broadcom generally refresh their SoCs about once a year to keep up with the latest requirements in features and interfaces, he added.

Intel execs indicated it might be six to 12 months before they update some of their 2008 SoCs. "Intel has to learn the SoC market is very fast paced," Gwennap said.

"Many of our tier one OEMs have not announced their products yet," said Rose Schooler, general manager for SoCs in Intel's embedded group. "It takes time for design wins and qualifications in comms, so I'm not surprised we're a year into this without public attributions," she said.

Intel's general manager for performance products, embedded group
Rose Schooler

An executive in Intel's consumer group said the TV business is also slow to adopt new chips. He said Intel has design wins for Canmore and its 45nm follow on—Sodaville--is well along in its design.

The recession has also cast a shadow on Intel's SoC plans. "We have had a program or two canceled by the economic environment, but we will continue our investment," said Schooler.

It's worth noting the Tolapai and Canmore parts were clearly early attempts. They were made in Intel's generic 90nm process technology, did not use its emerging SoC EDA design flow or its new internal fabric.

They also used an older Dothan-class Pentium M core, not the Atom, Intel's lowest power x86 core to date and the heart of all its future SoCs, including 45nm devices now in the works.

Thus Intel execs from Paul Otellini on down are keen to generate excitement about the 14 SoCs in design for the emerging 32nm process. It may take until those parts emerge in late 2011 before anyone can determine the impact the world's largest chip company will have on the SoC business.


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