Things change, things stay the same: Finding unity in a multi-faceted world

by Kenneth Larsen, Mentor Graphics , TechOnline India - June 28, 2011

As the industry moves from designing devices with relatively limited functionality to complex, multi-functional and networked devices, traditional techniques, such as simulation, are coming up short for full-chip verification.

The rapid escalation of what we do and what we can do with electronic design inspires a breathless pursuit of higher verification productivity. As the industry moves from designing devices with relatively limited functionality to complex, multi-functional and networked devices, traditional techniques, such as simulation, are coming up short for full-chip verification.

This is not only because designs are too big, but also due to complexity and how things interact. A cell phone is the common and appropriate example of multiple function systems. To test all the simultaneous operations that can occur together as a system cannot be done the old way. To keep up, companies must take a holistic view of verification during chip, system, and embedded software development.

The emergence of the SystemVerilog standard reflects this trend. SystemVerilog and SystemVerilog testbench methodologies make verification engineers more productive because they can generate reusable testbenches and automated tests faster. This is why we have seen a significant increase in the adoption of SystemVerilog in the creation of test environments and testbenches. Soon we’ll see an even bigger leap forward.

With the recent release of the Accellera Universal Verification Methodology (UVM), verification engineers can be more productive in terms of testbench reuse and test generation. The standardized, UVM class library provides the building blocks needed to more quickly develop well-constructed and reusable verification components and test environments in SystemVerilog.

However, for UVM adopters to be as productive as they need to be, they must break through the glass ceiling of simulator performance. This can be accomplished by enabling the same test environment used in simulation tobe run on an emulator, without modification. Pairing UVM testbenches with co-emulation enables significant verification productivity improvements in terms of raw performance, resulting in a dramatic speed-up in test execution.

The ability to reuse a single testbench for simulation and emulation is a major breakthrough because the RTL for complex or multifunctional designs will slow down a simulator to the degree that it’s not practical to simulate. The designs are too deep, the tests take too long. On the other hand, a hardware verification computing solution will run a test set in minutes that would take a week on a simulator. All the advanced verification techniques can be run on the emulator, including all the features that TLM2 delivers. All these things stay the same on the emulator but run extremely fast.

A single testbench shrinks the time and effort typically put into creation (because you create it once and only once), maintenance, and ongoing support for verification environments. And t extends reuse to multiple dimensions, as the same test environment can be used on next-generation designs. So companies get the dual benefit of reuse and simulation acceleration. A single test environment also produces consistent results because the tests behave the same whether they are on a simulator or an emulator. Without a single testbench, you might not be testing the same things so the results are inconsistent. By using UVM and SCEMI 2 on a Veloce emulator, users get an environment that’s consistent and results that are functionally equivalent.

Five years from now people will still be simulating, but they will not be simulating large systems. These are going to be simulated using hardware emulation. The goal is faster end-to-end verification of the entire development process. Leading semiconductor and electronics systems companies already embrace the technical and economic benefits of emulation. A hardware verification computing solution, like Veloce, that offers a single, reusable testbench for simulation and emulation will ease the path to wider adoption of emulation and increase its value.

Mentor Graphics has allowed its customers to take the whole UVM test environment, keep everything the same, and gain a dramatic boost in raw execution performance by going from simulation to emulation with minimal effort.

Some things stay the same, some things change. If you are thinking about UVM, we can show you the way to make the productivity improvements of the UVM much greater. So don’t start without us.
Abour the author:

Kenneth Larsen is the Technical Marketing Director for the Emulation Division at Mentor Graphics, Corporation. He has over twenty years of experience in electrical engineering and holds an engineering degree from Denmark.


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