To reduce the design and packaging cost, SoCs are usually developed satisfying a superset of demands of multiple customers. To target the customers who do not need the complete functionality the usual solution is to offer them only a subset of that functionality through the judicious use of packaging and pin out options. This, however, leads to inclusion of logic which might be needed by one customer and not by others.
A byproduct of this strategy is that the extra unused logic is not used in the lower functionality variants of the SoC and still contributes to the overall leakage. This is because it still also shares the same power network as the rest of the logic. Described here is a way to use power domain partitioning to reduce the leakage in lower variants by taking advantage of package configuration information.
The basics of chip-level power management
As per Moore’s law, we know that as the feature size has been scaled down the average chip size has increased over the period of time as indicated in the Figure 1 below:
Figure 1: IC transistor feature size has decreased and number of transistors per chip has gone up, but in relatively higher proportion. (Source www.ieee.org)
This indicates the intent of incorporating more and more functionality into a single SoC, which leads to to increased complexity, production cycle time and thus the associated development cost. The cost involved in the development, packaging and activities related to ‘Ramp To Production’ constitute a major portion of the total cost.
One common way to deal with this problem is to come up with an overall SoC design which meets the superset of all customers’ requirement and then to market to the specific subsets within it with limited functionality devices, through judicious use of various packaging and pinout alternatives.
Figure 2 below shows an example of the same, where a single die is shown to be packaged into three package variants. While the higher pin package provides all (or most of) the functionality, the smaller pin packages provide just right functionality. Thus, we can control the available memory, supported communication protocols, peripherals, ADC/DAC channels etc to a customer who does not seek them.
Figure 2: An example of a die going into different package variants
Motivation for saving leakage power
This technique enables us to develop a single SoC and sell multiple variants to various customers and also reduces the design cycle turnaround time. But the strategy calls for the integration of more logic/ IPs than required for a limited variant, with the result that the customer/user has a substantial amount of ‘phantom Logic’ sitting on the SoC.
Because, though unused, these phantom devices are still powered up and tend to leak and increase the leakage power budget. As we run more and more devices on battery, the leakage budget tend to be differentiating factor compared to alternative, but similar solutions.
Since it is still necessary to power up these phantom devices, they add up to leakage statistics that may reduce the competitiveness of an otherwise brilliant design. A comparison of leakage numbers for 3 devices of same family (MPC522x) which are available with different RAM and flash size configurations is provided in the Table 1 below:
Table 1: The STOP3 mode current is same for all the packages.
As the leakage numbers (STOP3 Mode) are same it can be inferred that the phantom devices do nothing but ‘leak’ in the limited functionality variants.The figures in red indicate the possibility of saving the leakage power. These numbers are huge. For example., the phantom device with 32KB of RAM, and with 256KB of Flash could have saved roughly 25% of the leakage current, in comparison to the device with highest amount of memories.
Saving Leakage Power for Phantom Devices
We suggest one way to handle this is through the judicious use of power planning, by "turning off" the power of the phantom logic in lower functionality variants, which would allow us to substantially improve the leakage budget. If a considerable amount of logic is expected not to be used in a particular variant of the SoC, why not power it with a different power network which could independently of the others be turned off.
One mechanism that could be used to achieve this is the dedicated IO pads most SoCs have, called the Device Configuration Pads (DCP) which give out DEV_CFG signals indicating the package type - such as, for example, 256 MAPBGA, 169 LQFP etc. These IO pads are hard-wired to and the device management logic monitors the DEV_CFG signals to detect the package type. An example of this is provided in the Table 2 below:
Table 2: Three (3) bits of DEV_CFG are used to differentiate between various package/ device options
The control circuitry uses this information to implement features like disabling or altering the supported peripherals, communication protocols, memory mapping etc. We propose the use of those same signals to implement a power management protocol (PMP).
First, though it is necessary to do some intelligent power planning and create different power islands, placing functional blocks - such as the logic/memories/IPs not used in lower functionality implementations in lower pinout packages - on a different power island.
Some caution needs to taken while doing this as the logic should be sufficiently high to qualify as power island. If the logic is very small it might not give a substantial leakage reduction in comparison to overheads related to power planning itself.
Once the power planning is done we use the DEV_CFG signals from the Device Configuration Pads (DCP) to implement PMP. These signals are fed into an improved power monitoring and control (PMC) logic block. In addition to the different power islands it also implements the PMP we defined earlier, as shown in Figure 3 below.
Figure 3: Power Management Protocol control logic
The PMC contains a voltage regulator to generate various supplies. Its different supplies can be switched OFF based on DEV_CFG. PMC generates ISO signals for respective power supply and also accepts ACK from the IP’s before gating power. ACK is required so that any tree of clock/reset which flows through these IP’s sequentially are properly bypassed or de-selected before power gating is applied.
The PMC of the system will receive device configurations from Flash at power up. The PMC will generate a CLOSE/ISO signal to the IP’s to be power gated (to make the IP aware that it is going to be shut down). This will happen during power up itself. After [solating all the interface to core, the IP will generate an ACK (Acknowledgement Signal) to PMC, stating it is ready for Power Down. The PMC will then shut-off the Power of the IP by means of an improved Voltage Regulator (VREG) design shown in Figure 4 below.
Figure 4: Improved VREG Design for power partitioning
Normally, POWER1 is always on while POWER2 and POWER3 are switchable depending upon DEV_CFG from flash and ACK from the relevant IPs. In Test mode, VREG_BYPASS=0 thus all supplies are ON during ATPG and other test modes. The VREG contains a basic error amplifier and an NMOS operating in saturation region.
In a slight modification to that taken in traditional designs, we here suggest having switchable power fed by the PMOS transistor operating in the linear region. Since the PMOS devices will be operating in the linear region, they can drive large currents without having much impact on the area of the logic required. The VREG bypass mechanism used during ATPG is also shown in the Figure 4 above.
Test Cost Reduction
This kind of power island partitioning can help in test time reduction for the limited versions of the SoC, since we need not test the logic functions not used on any particular package and inout variant. This strategy helps to bring down the overall cost, a major consideration in any design.
In most cases we try to test the various IPs of the SoC in parallel so as to reduce the test time. But, the major hurdle in reducing the test cost is that involed involved in testing NVM flash which can make up to 70% of the overall test cost. In Figure 5 below, a comparison of the test cost is provided, which clearly indicates the significant cost involved in testing the NVM flash.
Figure 5: Test time breakup for an SoC (To view larger image, click here).
Even here, costs can be reduced because it is now possible to create multiple variants of a SoC which have limited flash options. If the test can be done while avoiding the unused flash, the test cost can be reduced considerably. The unused flash can be put on a switchable power island which is turned off for the limited version.
Similarly, we can reduce the test time for ‘phantom logic’ by having two separate scan chains. One scan chain will test the part of logic which is active for all the variants and another which is specific to a variant. Figure 6 below illustrates this. In this case, the scan chain SI0-SO0, which is not available for a particular device configuration, and, so, can be turned off and the testing is avoided for Module ‘A.’
Figure 6: Two independent scan chains for different power modules in different device configurations.
We think that the technique described here can be utilized in all SoC with multiple device configurations to reduce the leakage power. But it will involve the redesigning of existing PMCs to incorporate the Power Island concept.
A necessary prerequisite of for success with this technique will be the intelligent power domain partitioning of various digital modules, and memory modules based on different device configurations.
About the author:
Kushagra Khorwal received his Masters in VLSI Design from GGSIP University in Delhi. Currently, he is working with Freescale Semiconductor, Noida, India as a Senior Design Engineer in the field of SoC Physical Design.
Abhishek Kumar received his Bachelors in Electronics Engg from DCE, University of Delhi. He is working as a Analog Mixed Signal Design Lead with Freescale Semiconductor, Noida, India. His main focus areas include Low Power VLSI Design, Mixed Signal Designs, ESD, EMC etc.
Shailesh Kumar is Physical Design Engineer with Microcontroller Solutions Group, Freescale Semiconductors, IDC Noida. He is responsible for backend activities like floorplanning, power estimation/analysis, and physical verification. He has been associated with Freescale Semiconductor for about 5 years.