Application specific integrated circuits (ASICs) typically conjure up the notion of massively complex logic chips containing tens or hundreds of thousands (even millions) of transistors configured to solve a customer’s unique set of problems. Unlike multi-function standard product ICs such as a micro-controller that can find its way into a wide variety of applications, ASICs are designed for one specific application and generally for one specific product or product family.To better understand the role and applicability of ASICs, it is important to briefly review their historical origins.
The first integrated circuits from the early ‘60s contained just a few transistors and performed simple digital logic functions such as "and", "or", "nor", etc. These were called SSI devices, meaning small-scale integration. As photolithography techniques improved, more and more transistors could be built on a single sliver of silicon. Soon, chip companies were developing medium scale integration (MSI) functions like flip-flops, buffers, latches, etc (10-100 transistors). Large-scale integration or LSI (100-1,000 transistors) and eventually VLSI (up to 100,000 transistors) ICs followed, providing lower system costs and higher levels of performance. Today, of course, we have digital chips in excess of a billion transistors thanks to advanced sub-micron lithography and the low voltage, high speed processes upon which they are built.
The first digital ASICs were built using a standard cell library consisting of fixed-height, variable-width ‘tiles’ containing the digital logic functions discussed above. The ability to reuse these blocks over and over saved time and money when designing a custom logic IC. Analog ICs were initially comprised of a pair of matched transistors and soon expanded to include rudimentary op amps, voltage regulators, comparators, timers and much more.
Demands of analog
Analog applications typically involve much higher voltages, so these ICs needed their own unique set of manufacturing processes. More recently, market demands for smaller size, higher speeds and lower power consumption have forced a merging of analog and digital functionality on a single silicon chip. Cells consisting of the basic analog building blocks discussed above were created and added to the digital libraries. These Analog cells were restricted to the digital fab processes developed for predominately logic applications.
Today, most ASIC companies offer some degree of analog functionality as a part of their services. In many cases, the analog functions are mimicked with digital design techniques. In others, compromises to the analog functionality must be made to facilitate the use of standard library cells that are designed to yield well in the fab processes developed for high speed, high density, low power digital designs. Often, these chips are referred to as Mixed-signal ASICs or as big “D”, little “A” ASICs, meaning high digital content and minimal analog content.
Analog ASICs play a critical role in our lives. Without them, none of the portable electronic devices we use in our daily lives would exist. Imagine a world without cell phones, MP3 players and navigation systems. Building them with standard products would make them prohibitively expensive and physically impossible to carry in our purses or pockets. Every automobile contains dozens of ASIC chips for everything from climate control to airbag deployment; suspension control to entertainment systems. ASICs also play important roles in applications for hospital medical equipment, eMeters, home appliances such as washers and dryers, scuba gear, hearing aids, and much more.
Picking an ASIC design partner
The analog ASIC market is huge. In fact, research firm IC Insights reports that almost 60% of the nearly $37B of analog ICs sold in 2010 were ASICs. Yet very few mixed-signal ASIC design houses fully understand the implications of custom analog design and its applicability to analog-centric ASICs. ASICs requiring high analog content should be directed to those design houses that specialize in analog circuit design rather than those who simply select analog IP blocks from a library. Analog ASIC companies have large staffs of competent, experienced, analog engineers with expertise in a wide range of analog functions.
Reviewing an ASIC house’s patent portfolio as a quick guide as to the creativity of its engineering team will serve as a first order measure of its analog expertise.
Clearly, the large analog IC houses (like ADI, Linear Tech, Maxim, National, TI) have patent portfolios a mile deep. Those that also engage in analog ASIC development set high bars regarding who can access this capability and impose high minimum order requirements. For example, TI reports that their application-specific analog business focuses on a small number of large customers like Seagate, Sony, Samsung, Hitachi Global Storage Technology, Toshiba and a few others that require custom application-specific products. Minimum annual unit and or dollar volumes force the majority of the smaller customers to seek out independent analog or mixed-signal ASIC design houses.
Myth#1: It is only economical to integrate analog functions into an ASIC if the analog content is minimal.
The ASIC concept began as an integration tool to lower the costs of computationally heavy logic circuits. Today, after 30+ years, ASICs remain heavily digitally oriented. When we hear the terms like SoC (system on chip) and re-useable IP (intellectual property) associated with ASICs, we often think of the massively complicated, digital centric ASICs that may contain a few important analog functions. Historically, it is these products that have garnered the attention of the media and established a mind set among the user community that a little analog can go a long ways. But what about the applications requiring analog-centric ASICs? These are SoCs as well, even though they may not contain a uP core or even memory.The medical/industrial world is rife with such requirements yet most ASIC companies are quite unprepared for the challenges of hand-crafting the unique Analog circuitry required for these important applications.
Throughout the world, and in particular in Silicon Valley, there are numerous ‘boutique’ wafer fabs that specialize in analog processes and are not loathe to accepting lower volume business. Considered a well guarded secret by many, these fabs welcome low and moderate volume analog business and offer pricing quite competitive with the billion dollar fabs in Asia. These smaller fabs have come to realize that while analog designs are often focused on lower annual volumes, analog in general has shown to be less susceptible to the violent supply/demand curve swings inherent to the general semiconductor industry. An additional attribute is that often analog chips can sometimes remain in production for as long as ten years or more. For the fabs, accepting reduced annual volumes becomes an annuity that offers payback for years to come. Experienced analog ASIC companies have spent decades nurturing these relationships for their customers.
The actual manufacturing cost of the ASIC chip may imply a huge savings when compared to the collective costs of the ICs it replaces. However, there are other costs associated with the ASIC that must be considered and amortized over the life of the product. Non-recurring engineering costs, based on the complexity of the design as well as hard tooling costs such as masks and test hardware, can add a few pennies or a few dollars to the ASIC chip cost, depending on the complexity and lifetime volume of the device.
Incorporating elements into the chip that require more exotic processes for features like high currents or low noise or high frequency will increase the cost of all the elements in that chip.Therefore, it is as important to know what to incorporate into the ASIC as it is to know what should remain a discrete component. Interestingly, the use of multiple smaller, less complicated analog ASICs, differentiated by their manufacturing processes, can offer surprisingly stunning cost reduction results.
Most analog applications use a collection of passive elements and discrete transistors in addition to the ICs involved. Integrating as many of these components as possible to the ASIC often comes for free and can have a dramatic effect in lowering the end product’s total assembly cost. It is this potential total system cost saving that bolsters the justification to develop the analog ASIC.
Myth #2: Mixed-signal ASIC means the same thing as analog ASIC
While the term “mixed-signal” implies a combination of analog and digital circuitry on a single chip, there is a distinct difference in the skill levels required to combine library cells (analog and digital) on a silicon chip versus actually creating an analog design that uniquely satisfies all requirements of the specification. For many applications, analog library cells offer sufficient performance to meet the system requirements.
However, more and more frequently, the increased sophistication of the analog application necessitates designs that are truly ‘application specific’ and not a compilation of general- purpose analog cell blocks.
Like the big analog IC companies, true analog ASIC companies employ experienced analog designers who are artisans at analog invention. Many of them have spent years at the big analog companies, learning from the industry gurus. Be careful not to let a mixed-signal design house negotiate you away from your ideal specification. Close isn’t good enough...analog must be exact.
Myth #3: Only ultra-high volume applications can benefit from analog ASICs.
As noted earlier, many large semiconductor companies focus their ASIC efforts onto a handful of very large customers. Clearly, these are the privileged few and everyone else must seek out development and manufacturing partners that can and will match their needs. All full service ASIC houses have their own business criteria regarding minimum NRE, tooling and most importantly, annual volume. Some ASIC houses avoid the issue by just offering design services and leaving the issue of manufacturing to the customer. Either way, it is often the subcontract wafer fabs rather than the ASIC companies themselves that dictate minimum annual volume restrictions.
The semiconductor industry operates in alternating cycles of boom and bust. A brief look back in time reveals that in boom times, capacity at the big Asian foundries fills quickly and all but the most promising, high volume customers are turned away. Aggregators have somewhat mitigated the problem by combining numerous smaller company requirements under the umbrella of their larger purchasing power. However, the large Asian fabs are built to benefit from economies of scale, offering processes tailored for the mass market; high density, lower power logic. For many, analog is problematic. Fortunately, there are bountiful alternatives.
Myth #4: Using existing IP from analog cell libraries lowers the chip cost.
Using predesigned, functional cells such as amplifiers, converters and transceivers can shorten development time and therefore has a ripple through effect of lowering the chip’s total cost. However, even though design time is reduced, there can be other tradeoffs that must be considered. Standard analog library cells do not pack as neatly as digital cells. Using Analog library cells can result in blocks of unused silicon on the die that will needlessly lower the numbers of potential die on a wafer.
Additionally, since the analog circuitry of a mixed-signal ASIC is likely to be the input or output of the circuit, or both, these cells must be oriented closer to the periphery of the chip to facilitate easy access to bonding pads.
Handcrafting some or all of the analog functions allows the designer to accomplish several things. In a Mixed-signal design, handcrafted analog circuits are laid out to fill voids created when using standard digital cells, better optimizing overall silicon area utilization.Moreover, handcrafting the analog portion allows the designer to determine precisely the performance parameters of the circuit rather than be restricted to the fixed performances of a limited number of standard cells available in the library.
The conundrum of using overdesigned cells is another consideration worthy of the designer’s attention. As an example, for a given application, some analog parameters may be able to be relaxed, simplifying the handcrafted design compared to a standard cell. Alternatively, handcrafting the Analog circuitry affords the designer an ability to improve other performance parameters that can have far reaching implications that make the ASIC less costly in terms of test yield and thus more competitive in the marketplace.
Myth #5: Cell-based ASIC designs ensure product differentiation
Designing the analog portion of a mixed-signal ASIC using a cell library is tantamount to designing a system using standard, off-the-shelf, analog ICs...with one key exception...selection. At the board level, there are tens of thousands of IC amplifiers, voltage references, converters and more from which to choose. In a cell library, the designer is limited to choosing from to a few of dozen amplifiers, voltage references, converters, etc. Performance compromises may be needed to accommodate these limited choices.
Analog-centric ASIC development affords a perfect opportunity to rise above the competition. As noted earlier in this paper, nearly 60% of the worldwide analog IC market is ASICs. If you and your competitors are basing your designs around the same Mixed-signal cell libraries, both of you will have approximately the same performance specifications, dictated by the specifications of the library cells. True product differentiation comes from invention. It is derived by creating uniqueness to a product not readily available to the competition. Cell libraries fail to deliver the necessary uniqueness often needed in critical analog applications.
Myth #6: Handcrafted analog is too expensive, compared to standard cells.
There is a time and place where standard analog cells are more than adequate. Experienced analog ASIC design houses recognize this and only offer full custom Analog Design when the need merits it. Handcrafted analog can create the differentiation required to break out of the pack with a superior performing chip and thus a superior end product for your customer. Additionally, stepping back from the cell library approach opens up options for manufacturing, since cell libraries are typically developed for one process at one fab. Broader use libraries are available that specify a process, for example, 0.35um CMOS, but have relaxed specifications such that they can be instantiated in multiple fabs.
Handcrafted analog creates an unlimited set of manufacturing options, especially through the use of boutique foundries. Many of the boutique fabs differentiate themselves by the variety of services they offer and their willingness to make adjustments to their processes to accommodate optimization of the chip’s performance.
A recent example is a circuit we developed for a major automotive component supplier. The chip required a high voltage MOSFET that was not available in the boutique foundry’s standard process. Integration was critical to the success of the project, so the foundry and JVD worked together to create the needed device structure. The subsequent design provided the high voltage robustness needed for the application while minimizing parts count and the physical size of the end product.
NRE costs are a compilation of several variables. These costs must be amortized over the number of chips produced during the lifetime of the product to determine their effect on the unit cost of the ASIC. When executed properly, NRE costs associated with handcrafting the Analog circuitry return a disproportionately lower unit cost of the final chip. The key to success is analog Design experience resident at ASIC House doing the integration.
Myth #7: The most cost effective solution is to pack as much as possible into the mixed-signal ASIC chip.
In a recent posting on Linked-In’s Global Semiconductor Alliance GSA Networking Group Discussion page, an IP market analyst commented on the difficulty of integrating customer specific analog into a predominately digital design, citing the need to have 3 or 4 preproduction runs. The product, an SoC for a PalPlus TV system, missed its release date by more that 1 year.
This case shows the problem clearly. Insufficient analog expertise can get a mixed-signal ASIC house and their customers into a real bind. Missing a product launch window by a year or more is the kiss of death. When the Analog component of the design is critical (for example, more than a basic A/D or DAC) it’s best to seek out analog ASIC experts to perform the integration.
Moreover, splitting the functions into multiple chips should be considered when both the Analog and Digital content is excessive. The fact remains, analog circuits perform better in non-digital fab processes. When possible (from a cost/yield/board space perspective) the long-term cost benefits of a dedicated analog ASIC chip can be overwhelming.
The application will always determine the appropriate combinations of technologies that are best suited for the ASIC design. As our dependence on cognitive prosthesis devices (smart phones, Wii controllers, tablet PCs, etc.) increases, copper tethers disappear and analog increases its dominance in ASIC designs. MEMS advances have placed Star Trek style sensors in our daily lives. Medical imaging, sensing and monitoring continues to improve our daily lives. All of these and more increasingly rely upon better, faster, denser analog circuit content.
When considering a new ASIC design, carefully consider the role analog will play in its deployment. To minimize risk, choose your ASIC development partner carefully. Most of the time, mixed-signal ASIC design skills will be sufficient. To minimize risk, seek out an analog ASIC partner with the right analog design skills and experience to match the application.
About the author:
Bob Frostholm is Director of Marketing at Analog ASIC company, JVD Inc.
(San Jose, CA.) www.jvdinc.com. Bob has held Sales, Marketing and CEO roles at established and startup semiconductor companies for more than 35 years and is the author of several technical articles and white papers. Email: firstname.lastname@example.org
This is an excerpt that contains the vast majority of a white paper by Bob for JVD. You can find the full text with additional graphics at: http://www.jvdinc.com/mixed-signal-asics.php