PCI Express will scale to 8 GHz by next June

TechOnline India - July 15, 2009

The final specification for PCI Express 3.0 will be released by next June, the PCI Special Interest Group announced at its annual conference, providing more detail about the 8 GHz interconnect and challenges implementing it.

SANTA CLARA, Calif. — The final specification for PCI Express 3.0 will be released by next June, the PCI Special Interest Group announced at its annual conference here. PCI SIG members also provided more detail about the spec, suggesting some of the challenges companies will have implementing the 8 GHz interconnect.

Meanwhile, engineers are also working through new challenges using the virtual I/O standards the PCI SIG released at its conference last year. And others are working on an updated version of a PCI Express cable supporting data transfers at up to the 5 GHz rate of PCIe 2.0.

"The big news is PCI Express version 3.0 will be available in the first half of next year," said Al Yanes, president of the PCI SIG in a press briefing here.

Al Yanes
PCI Special Interest Group

The new interconnect is expected to start shipping in systems in 2011. It initially will be used for bandwidth-hungry graphics chips in high-end desktops and in servers using multiport 10 Gbit Ethernet and 8 Gbit Fibre Channel cards.

The spec is expected to be in a version 0.7 this quarter. From that point, engineers will be running simulations and test chips to validate theoretical models of the technology. A separate test specification is also in the works.

When the work is complete, the 8 GHz interconnect is expected to be compatible with the previous 2.5 and 5 GHz versions and use the same connectors. It also is expected to support the existing PCIe bit-error rates and the reach of up to 20 inches and two connectors for servers.

The SIG chose 8 GHz rather than 10 GHz for PCIe 3.0 as a power saving measure. The additional equalization required to hit 10 GHz would have required "exponentially" more power, Yanes said.

"The power shot off the roof," in 10 GHz PCIe simulations, he said.

That decision forced developers to use a more aggressive 128b130b scrambled encoding scheme to maintain a doubling of throughput for the new generation interconnect to a Gbyte/second per lane in a single direction. The new encoding approach has just 1.6 percent overhead on data transmissions compared to 20 percent for the existing 8b10b encoding scheme.

{pagebreak}Supporting the new encoding scheme and maintaining backward compatibility to the earlier versions of the spec are the two chief implementation challenges engineers face with PCIe 3.0, Yanes said.

Indeed, one test engineer said it is requiring significantly more gates in the FPGA his company uses in a protocol analyzer. For example, just finding the start of a new byte is a more complex task, he said.

Supporting the new and old encoding schemes may force some designers into using two physical layer cores arbitrated by a switch. Products will at least have to support two phase-lock loops to handle the 8 and 5/2.5 GHz clocking.

Thus PCIe 3.0 chips are expected to require at least a 65nm process technology. "We don't envision people using 90nm," Yanes said.

It's not clear yet what levels of equalization the new spec may require. Gennum Corp. announced earlier this year it is licensing silicon controller and physical-layer blocks for PCIe 3.0 that use five-tape decision feedback equalization.

Motherboard makers will still be able to use four-layer boards for PCIe 3.0 designs. However they may need to adopt new trace routing techniques and face impedance margins tighter than today's 85 Ohm limits.

Both PCIe versions 3.0 and an updated version 2.1 support a handful of new features. They include atomic operations, TLP processing hints and ID-based ordering capabilities that will be particularly helpful for handling parallel operations in multicore systems.

Yanes said he was not aware of any more aggressive features in the works for PCIe to support emerging parallel programming constructs still in an early research phase. One source said Advanced Micro Devices and Hewlett-Packard have proposed multiplexing extensions for 3.0, but the proposal has not been released or voted on by the PCI SIG board yet.

At the conference, Synopsys Inc. announced it has released PCIe 3.0 controller, physical layer and verification blocks to early customers. Cadence and nSys Design Systems also announced verification IP for PCIe 3.0. For its part, Synthesis Research Inc. announced an integrated test bench to handle transmitter and receiver testing for the earlier 2.5 and 5 GHz versions of PCIe.

{pagebreak}Separately, an Intel engineer said he is working with I/O chip and card makers to get them to support the PCIe virtual I/O specifications released last year. The specs let a single networking or storage controller handle as many as 128 virtual function without going through operating system routines.

However, engineers need to work closely with the hypervisors from virtualization software companies to implement virtual I/O under PCIe. That's because the PCIe spec does not address issues at the upper layers of software where the virtual environments operate.

Networking startups such as NextIO and Neterion have made strides supporting PCIe virtual I/O. However, most support to date has been for the so-called single-root version (SR-IOV) of the standard that works within a single system. A multi-root version (MR-IOV) for sharing I/O between different systems has yet to see significant adoption.

Big computer companies have long had their own proprietary approaches to virtual I/O, but they are beginning to adopt the PCIe standards.

"We are going to use SR-IOV," said Yanes, a chip designer for IBM's Power-based servers.

Industry adoption for MR-IOV "hasn't been as fast," he said. "We have to get SR-IOV going first in full adoption mode and then maybe MR-IOV will come along," he added.

The Intel engineer expressed skepticism MR-IOV would gain market traction given it is limited to a relatively narrow niche of server blade systems.

Meanwhile, a PCI SIG working group is meeting weekly to hammer out the definition for a cabled version of PCIe running at up to 5 GHz. It is expected to be complete by June 2010 and support distances up to five meters. A 2.5 GHz version already exists supporting distances up to seven meters.

The 5 GHz cable is initially aimed at linking multiple I/O chassis for servers or linking to an external graphics subsystem to high-end PCs. The spec is currently in a version 0.5.

"Once you build it, people will come," said Yanes of the 5 GHz cable interconnect. "This is a very promising technology, and there is a lot of member interest in it," he added.

Given the downturn, the PCI SIG waived the cost of the conference for attendees which attracted 350 engineers. Yanes said the PCI SIG's membership levels and finances remain healthy despite the downturn.

"We are OK, but a lot of other standards organizations are having struggles," he said.


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