Over the past 40 years, the semiconductor industry has continued its rapid pace offering more compact electronic products with higher speed and increasing functionality at lower cost. This rapid growth has been fueled by the industry’s ability to scale MOS transistors as predicted by Moore’s law.
Yet, when technology nodes have reached the sub 90-nm threshold, performance improvement anticipated from scaling failed to match expectations within the analog design community. This is largely due to the emergence of Well Proximity Effects (WPE) and Shallow Trench Isolation (STI) stress effects that were not accounted for in previous process nodes.
WPE and STI related stresses have been proven to severely disrupt the electrical characteristics of MOS devices. Such effects depend on device placement during the layout design phase, hence the more generic description: layout-dependent effects (LDE). LDEs affect a device’s intended performance and subsequently disrupt system functionality. For this reason, careful handling of these effects at advanced process nodes is necessary to guarantee a design’s robustness.
At nanometer process nodes, analog behavior is highly sensitive to layout interdependencies that rapidly cause intolerable device mismatches —a 10–15% shift in threshold voltage is a common occurrence if LDEs are ignored. However, the associated impacts of these effects on a design’s performance can be seen only after the complete layout is finished; i.e. at the end of the design cycle, which leads to many design iterations. Thus, to reduce these costs and ensure parametric yield at these deep submicron levels, analog designers cannot wait until post-layout verification to analyze layout-dependent effects. Instead, a fusion between electrical and physical effects is needed during the early circuit design cycle.
Unfortunately, today’s class of EDA tools does little to help preserve the designer’s intent against these types of complexities. Designers need layout-aware schematic-level design methods and tools that allow them to access and analyze transistor non-idealities caused by the proximity of neighboring devices and structures in the layout.
A look at the conventional custom IC design flow and its LDE associated challenges gives us some insight to why this new tool and methodology is critical to reducing the design cycle. The conventional design flow can be divided into two phases: a front end, which starts with circuit schematic design followed by performance verification through simulation, and a back end phase, during which the layout is created through placement and routing, followed by a physical verification step that results in the extraction of a parasitics-annotated netlist. This back-annotated netlist is re-simulated to check for possible deterioration of design targets.
Figure 1: Conventional custom IC design cycle.
More often than not, deviations from the original design targets take place, which calls for several iteration cycles between the front-end and back-end phases until the design finally converges on the spec. Such deviations are mainly due to both LDE effects and routing parasitics. In above 90nm technology nodes, the LDE effects were considered second order effects. The main layout challenge was focused only on reducing routing parasitics. However, below 65nm, layout-dependent effects have a significant impact on a device’s threshold voltage and carrier mobility, which degrades device matching and, hence, overall design performance. Solving these LDEs usually requires replacement, or at least shifting locations of some devices, which then requires re-routing and, hence, increases the complexity of each design cycle.
A promising and innovative solution is interactive LDE estimation. During custom layout creation, interactive LDE estimation finds the deviation from nominal values of the threshold voltage and the drain current for each transistor. When the allowable ranges for such parameters are already known, possessing this information gives layout engineers the knowledge to achieve optimum device placement with respect to circuit performance. Without resorting to any performance simulation, the layout engineer is now able to see the magnitude of such deviations when any of the devices are moved. Hence, device placement with minimum impact on design performance can be easily determined in an efficient way.
During custom layout design, an interactive layout-dependent effect estimation tool is able to quantitatively estimate actual threshold voltage and current deviations from intended values resulting from a given device placement in an interactive manner. This can be more valuable if the circuit designer provides permissible ranges and constraints on transistor threshold voltage and current for critical devices. This solution provides layout design engineers with an interactive estimator for the LDE impact on electrical device behavior while taking device placement decisions. Accordingly, LDE impact on overall design performance can be minimized before starting the routing step.
How It Works
To show how this new approach operates, we will present an example design of a simple two-stage Miller OTA amplifier, as shown in Figure 2, which uses a 65nm technology. To simplify the demonstration, the solution will focus on the WPE effect. However, the same concepts can be easily extended to consider other LDE effects; such as STI effects.
Figure 2: Schematic design of two-stage Miller OTA, biasing network not shown.
Figure 3: The new proposed custom IC Design cycle.
As shown in Figure 3, the design flow, including the interactive LDE estimator module, is as follows:
1. Schematic design and functional verification takes place until the design requirements are met.
2. Operating point information, from circuit simulation, is collected together with device constraint data (optional) for future use by the LDE estimator module. Device constraints include the allowable variation of threshold voltage “∆Vth” and current drive “∆I”. Device constraints can be mostly determined based on the designer’s expertise. These constraints can also include matching between selected devices.
3. The layout engineer performs layout placement according to the minimum design rules, targeting area optimization.
4. The layout executes the LDE estimator module which will do the following steps:
a. Extract the layout dimensions required for the WPE calculations.
b. Pass the WPE dimensions to the LDE checking module that calculates the deviation of the Vth and I of every device. This checking module includes BSIM4 WPE equations that determine the changes in threshold voltage and mobility parameters and a simplified current equation based on a BSIM4 model. This step does not require circuit simulation and uses the OP information collected in an earlier step.
5. If ∆Vth and ∆I are not meeting the pre-defined constraints, then the layout engineer has to move layout devices and check their new ∆Vth and ∆I using the LDE estimator module until the constraints are met; in this case, the placement step will be concluded, and the layout engineer will start the routing step. It is important to note that this method does not require circuit simulation during the interactive LDE estimation step and minimizes the design targets dependency on LDEs before proceeding with the routing and physical verification steps.
Now we will validate whether this LDE estimation flow produces good results. To do so, we used the same Miller OTA design and the Pyxis, Eldo, and Calibre IC-design tools from Mentor Graphics.
First, the schematic design has been tuned to obtain the targeted Gain and Bandwidth as depicted in the simulation results shown in Figure 4.
Figure 4: Bode plot for the OTA design.
Second, layout devices are placed according to the minimum design dimensions as shown in Figure 5. On checking the simulation results based on extracted layout, without taking the interconnect parasitics into account, the design targets (Gain and Bandwidth) failed because of the LDE effects, as seen in Figure 4.
Second, layout devices are placed according to the minimum design dimensions as shown in . On checking the simulation results based on extracted layout, without taking the interconnect parasitics into account, the design targets (Gain and Bandwidth) failed because of the LDE effects, as seen in .
Figure 5: Layout on the minimum design dimensions.
Then using the LDE estimator module, as explained before, we were able to reduce the value of the ∆Vth and ∆I (as seen in Table 1) by moving devices around and figuring out the best layout placement that guarantees smaller deviations from the design targets, as seen in Figure 6.
Figure 6: The layout after using the LDE estimator.
Table 1: ∆Vth and ∆I values before and after using the LDE estimator module.
Finally, checking the simulation results of the final layout, without routing parasitics, the Gain and Bandwidth are very close to the original pre-layout simulation.
This new approach for estimating LDE effects at an early phase of the design cycle reduces the design cycle significantly. Using the LDE estimator module, users can quickly learn how to achieve better layout placement and boost overall productivity despite LDE snags.
The continual shrinking in layout dimensions has given rise to significant effects that carry interdependencies between neighboring structures. During the past few years, technologists have demonstrated STI related stress to severely disrupt the analog characteristics of MOS devices and, thus, the overall circuit functionality. Careful handling of these effects has therefore become an essential requirement for guaranteeing design robustness.
This article discussed a new approach for estimating LDE effects at an early phase of the design cycle. The LDE estimator module introduced was demonstrated to be particularly valuable in bridging the gap between electrical design intent and physical realization. This methodology is expected to boost overall productivity despite the snags imposed by advanced layout dependent effects.
Article Courtesy: EDA DesignLine