Managing signal integrity in tomorrow's high-speed flash-memory-system designs

by Percy Keller , TechOnline India - July 20, 2011

Next-generation flash-memory technology will tout data-transfer rates as much as 10 times faster than currently available. However, increasing distortions in the data-carrying digital signals can cause data-transfer failures, complicating the management of signal integrity. Proper design strategies can help you deliver reliable, high-performance products.

Signal integrity will matter more in next-generation flash devices, and several changes in the technology will make managing signal integrity more critical. For example, data rates in these devices will range from 400 MHz to 6 GHz. To support the faster data rates, edge rates will have to become 10 to 100 times faster. Demand for increased storage capacity will also drive the need for denser packaging and more complex interconnects.

Pressure to reduce costs will force you to make trade-offs that affect signal integrity, such as using lower-cost materials or even eliminating the use of ground planes. As rise times become shorter, a signal’s high-frequency components become more pronounced. Higher-frequency signals are more sensitive to interconnect quality, so signal-integrity problems tend to proliferate. As signal frequencies increase, signal loss also increases. Therefore, high-frequency components of fast-rise-time signals experience more loss than the low-frequency
components, leading to signal distortion and ISI (intersymbol interference).

Signal-integrity problems

Understanding the causes of signal-integrity problems and their remedies is critical. Signal-integrity problems include reflections and distortions, crosstalk, ground bounce, and jitter. Reflections and distortions relate to signal quality on an individual net. When a signal encounters an impedance discontinuity, it generates a reflection that becomes further distorted as it continues along the net. The reflection travels from the impedance discontinuity in two directions—toward the

receiver and back to the driver. The reflections themselves react to other discontinuities, creating further reflections that distort the true signal in complex ways, generating effects such as ringing, overshoot, and slope reversal. Careful design to maintain well-controlled impedance along key traces is the best way to improve signal integrity.

Managing signal integrity in tomorrow’s high-speed flash-memory-system designs figure 1Crosstalk-induced signal-integrity problems involve multiple signal nets. If you place an active net near a quiet one, capacitive and inductive coupling can cause some of the energy from the signal on the active net to couple over to the quiet side (Figure 1).




The quality of grounding and current-return paths in your design is among the biggest factors affecting crosstalk. In most PCB (printed-circuit-board) designs, ground planes are available as return paths. This approach is best if you can afford the extra plane. If cost pressure forces you to eliminate using a ground plane, you must use  other strategies, such as placing a ground trace next to the signal or using differential instead of single-ended signaling.

Ground bounce also affects signal integrity and relates to power distribution. As with any network that has interconnects, inductance exists in power and ground networks. As the I/O signals transition from zero to one or one to zero, transient current flows in the power-distribution network. Many signals’ switching at once generates large transient currents. Any inductance or resistance in the power- and
ground-distribution network converts these transient currents into voltage spikes that appear as noise in other signals or even as a shift in the ground voltage. Ground planes or multiple ground or power connections reduce the impedance and therefore the SSO (simultaneous-switching-output) noise. Using lower voltage swings and protocols that minimize the number of signal transitions also helps.

Managing signal integrity in tomorrow’s high-speed flash-memory-system designs figure 2Jitter issues also affect signal integrity. Reflections, crosstalk, and SSO all can contribute to jitter. In addition, ISI created on lossy channels, PLL (phase-locked-loop) noise, EMI (electromagnetic interference), differences in transmitting and receiving threshold voltages, and ordinary delay mismatches in internal logic can generate jitter. The strategy for managing jitter differs, depending on the cause of the jitter. Proper shielding can help with EMI-induced jitter, but it cannot fix a noisy power supply. Knowing whether the jitter is random, periodic, or correlated to some other event in the system helps you determine the best ways to address the problem (Figure 2). 




Manage signal integrity in your designs

As every RF engineer knows, everything in a circuit can affect the signal. To manage signal integrity, it is critically important to first identify the parts of the design that affect signal integrity. A common approach is to start by creating a
model of your design and its components and interconnects. However, a model typically is less accurate than it needs to be. You must make measurements of your circuits, compare them with your model, and adjust the model to make it consistent with your measurements. Once the model is accurate, you can use the simulator to predict which changes will improve signal integrity. Pay particular attention to vias, wire bonds, packages, PCB traces, and connectors when considering components that will affect signal integrity.

The goal of simulation and modeling is to predict the real-world behavior of your design. Engineers have traditionally used modern design and simulation environments, such as Agilent’s ADS (Advanced Design System), for microwave and RF design. As digital speeds approach microwave speeds, engineers have been applying these tools to digital design, especially for evaluating signal integrity. These tools accurately simulate high-speed effects, such as distortion, mismatch,
and crosstalk, in your channels.

Managing signal integrity in tomorrow’s high-speed flash-memory-system designs figure 3Integration of system, circuit, and EM (electromagnetic) simulators provides accurate answers and avoids error-prone and time-consuming data transfer among point tools (Figure 3). The ADS model in the figure can assess signal integrity and predict eye diagrams at various nodes in the backplane. You can see the eye after the daughtercard, at the high-speed backplane connector, and after the backplane traces. From these eye diagrams, you can determine where signal-integrity problems caused the eye to degrade and at what point
you should modify the design. An accurate model such as this one gives you insight into your design and lets you rapidly evaluate changes that will improve its performance.

Physical-measurement tools

Making physical measurements is key to assuring the accuracy of your model and validating the final performance of your design. At the speeds of next-generation flash design, it is important to analyze the data in both the time domain and the frequency domain. You can make physical measurements with a time-domain instrument, such as a TDR (time-domain reflectometer), or a frequency-domain instrument, such as a VNA (vector network analyzer).




If you’re new to measuring interconnect behavior, you may want to consider starting with a TDR, such as the Agilent 54754A differential and single-ended TDR module. It provides an intuitive waveform and good first-pass model. For greater accuracy and higher bandwidth, you’ll need to learn S parameters and use a VNA, such as the Agilent N5241A.

Another possibility is to use tools such as Agilent’s PLTS (physical-layer test system). With the PLTS, you can work in either the frequency domain or the time domain, whichever best suits your requirements, regardless of whether you are using a TDR or a VNA (Figure 4).




As the signal travels through the physical structures, the TDR measures and displays impedance. Ideally, the impedance trace is a flat line, indicating no discontinuities. At the daughtercard via, you can see a large discontinuity, so you know you must modify your design to raise its impedance.

Managing interconnect design on PCBs

Active circuitry, packaging, and connectors all influence signal integrity; PCBs can also influence signal integrity, often in difficult-to-detect ways. Competing demands for high speed and low cost often collide on the PCB. For example, FR4 is low cost and has relatively good performance at lower data rates. However, when data rates exceed 10 Gbps, problems increase dramatically.

Figure 5 should help you identify which elements of your design might be causing problems and suggests ways to deal with those problems. The next generation of flash will enable next-generation performance, but next-generation speeds will require designers to pay increased attention to signal integrity. Understanding what can affect signal integrity and how to model and measure it will help you deliver reliable, high-performance products on time and on budget.




About the author:

Perry Keller is program lead for applications and standards at Agilent
Technologies, where he has more than 25 years of experience in software
and system engineering, high-speed-hardware and ASIC design and
validation, and product marketing. Keller has a master’s degree in
electrical engineering from Rice University (Houston).

This article first appeared in EDN on January 20, 2011













































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