Programmable oscillators enhance FPGA applications

by Sassan Tabatabaei, SiTime Corp. , TechOnline India - September 29, 2011

Programmable clock oscillators offer many advantages when used as timing references for FPGA-based systems, the main being design flexibility.

Today’s complex FPGAs contain large arrays of functional blocks for implementing a wide variety of circuits and systems. Examples of such blocks are logic arrays, memory, DSP blocks, processors, phase-locked loops (PLLs), and delay-locked loops (DLLs) for timing generation, standard I/O, high-speed digital transceivers and parallel interfaces (PCI, DDR, etc.). Often, these FPGAs use multiple clocks to drive different blocks, typically generating them using a combination of external oscillators and internal PLLs and DLLs. The system designer has to decide how to combine external and internal resources for optimal clock tree design.

Programmable clock oscillators offer a number of advantages when used as timing references for FPGA-based systems. Chief among them is the design flexibility that arises from high-resolution frequency selection for clock tree optimization. Anotherbig benefit is spread-spectrum modulation for reducing electromagnetic interference (EMI).

A silicon MEMS clock oscillator architecture that is inherently programmable solves many problems for system designers who use FPGAs. The architecture of this type of  microelectromechanical system can easily incorporate additional features such as spread-spectrum clocking for EMI reduction and a digitally controllable oscillator for jitter cleaning and fail-safe functions in high-speed applications.

Frequency selection

A typical system needs a number of clock frequencies. Some are standard, either because they are mandated by an industry specification – for example, 100 MHz for PCI Express – or by virtue of being used widely, such as 75 MHz for SATA or 33.333 MHz for PCI. Such frequencies are associated with I/O interfaces to ensure interoperability, because the two sides of theinterface may not belong to the same system. In contrast, the user may select the clock frequency for driving processors, DSP and state-machine engines to optimize for speed, power or resource usage.

When optimizing for speed, you should clock the processing engines with the highest clock frequency to maximize the number of operations per second. However, the clock period jitter must also be low to ensure the minimumclock period is greater than the critical timing path in the design; otherwise logical errors may occur. A common approach for frequency selection is to use internal FPGA PLLs to synthesize a higher-frequency clock from a standard external reference oscillator. This approach is

effective if the internal PLL has high-frequency resolution and low jitter.

Some FPGAs incorporate internal, low-noise fractional PLLs that meet all of these requirements. In this case, you can use a simple external oscillator reference. However, in many cases, FPGAs use PLLs with a ring VCO and integer feedback dividers to synthesize different frequencies. Such PLLs are small and flexible, relatively easy to design and control, and consume very little power. But when using these internal PLLs, it is difficult to achieve high resolution and low jitter simultaneously.




 Figure 1. Block diagram of a typical integer PLL


The general architecture of an integer PLL is shown in Figure 1. The PLL output frequency is programmed with a combination of predivider (P), feedback divider (M) and postdivider (N), as in the equation below:



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