Power-aware design-for-test (DFT) can save a significant amount of power during logic test by reducing scan shift switching. Test engineers use automatic test pattern generation (ATPG) to achieve maximum coverage with the fewest test patterns. This can conflict with power management because the IC is often operated beyond its normal functional modes during test to get the highest quality test results.
When switching activity exceeds a device’s power capability during test, it can have detrimental effects on the IC, such as collapse of the power supply, introduction of switching noise, and excessive current that could lead to joule heating and connection failure. These effects lead to false failures, and can damage IC in ways that decrease its lifetime.
When planning for power-aware test and creating production test patterns, several techniques should be used to manage power during test. Using the techniques outlined here, scan shift switching—the largest contributor to power usage during test—can typically be reduced from 50% (normal level as even distribution on 1s and 0s) to 25% with minimal impact on test time.
There are a couple of less sophisticated techniques that have traditionally been used to control power during production test: reducing clock speed and skewing the clocks. Reducing the clock frequency allows power to dissipate and reduces the heating and average power.
However, this could exacerbate a problem with instantaneous power because the circuit will settle more between the lower frequency clock pulses. Skewing the clocks such that they rise at different points within the cycle reduces instantaneous power. This technique is highly dependent on the clock design, does not help with average power, is circuit dependent and, in some cases will not address localized problems.
A more modern approach is to use modular test. A modular test approach manages switching activity during production test by sequencing test activity and controlling power on a block-by-block basis. This method requires configuring test pattern generation so that only active blocks are considered during the ATPG process and the remaining blocks are held in a steady state.
Figure 1 shows an example of a design that is partitioned into several modules. Each module’s scan chains are accessible at the top level.
Figure 1: A modular test approach manages switching activity by sequencing test activity and controlling power on a block-by-block basis.
Multiplexers are used to select modules targeted at a given phase of the test. The number of phases is determined by the switching activity limit and the coverage required. Their requirement may exceed the number of modules because of additional configurations needed to achieve coverage of the top-level interface logic. The block not being tested can be held in a steady state using clock gating, reset assertion, or steady-state scan.
A modular test approach is enhanced with block-based test compression insertion, which also improves top-level routing. The testability of an individual block is also improved with test point insertion and logic built-in self-test (BIST), potentially reducing the switching activity needed to reach target fault coverage.
Another useful technique is to manage switching activity during scan test with various ATPG strategies. In standard ATPG, pattern generation targets the maximum number of faults in the minimum number of patterns. This approach leads to high levels of switching activity, usually in the early part of the test set. But if you relax the rate of fault detection and set a switching threshold as part of the initial constraints for ATPG, the coverage rate is spread throughout the entire test set, leading to a lower average switch activity.
During the ATPG process, switching activity can be controlled by enabling power control, and setting switching activity thresholds for capture and shift. Without switching threshold control, switching activity for scan shift is typical 50% with capture activity up to 50% too.
A third technique to control test power is to use clock-gating to limit capture power by holding state elements that are not being used to control or observe targeted faults. ATPG controls the clock-gating logic with either scan elements or primary pins. Hierarchical clock controls can provide a finer level of control granularity while using fewer control bits.
Testing in the presence of multiple power domains
Power-domain gating controls are powered by switching off the supply to inactive portions of a design, which saves both dynamic and static power dissipation. In this operation mode, ATPG accounts for the power-control structures and generate patterns that operate within the confines of the selectable power configurations.
Because power-domain switching and the additional cells and structures used in its implementation can adversely affect scan operation and ATPG, new checks and rules need to be developed to ensure that scan testing is effective. Typical rules that need to be checked include:
- Correct definition of power modes
- Correct control of power modes
- Correct connection of scan path and control logic through multiple power domains
- Correct operation of the scan path through switchable power domains
- Correct control of power domains through scan load, capture, and unload cycles
Power-domain switching logic can be tested either by implication or direct observation. When testing by implication, the incorrect operation of a circuit within a switched domain has to be detected by cycling the power control logic while exercising the circuit within the switched domain so that an incorrect state on a retention cell within the domain can be observed. This method relies on retention cells being present and usually requires a complex ATPG test sequence.
The second, preferred method, is to insert an observe point at the output of the power control logic to explicitly detect a failure. Retention and isolation cells between domains can be tested by toggling power domains and checking that the appropriate values are observable at the block boundaries.
As with testing of the power-switching logic, this method requires both control of the switching logic and control and observability of the retention and isolation cells through scan elements. Level shifters can be tested with standard stuck-at and transition tests because they are effectively buffers with different input and output thresholds.
Scan shift switching can typically be cut in half with minimal impact on test time. Capture switching activity can also be significantly reduced, but is highly design dependent. Designs with well-structured data paths and hierarchical, fine grained clock gating schemes can achieve capture switching activity of less than 10% with no coverage loss. By leveraging features already in place at the system level to control power dissipation in functional mode, power used during production test can be effectively managed. When design-level approaches to power control are combined with ATPG and BIST techniques, you can achieve high-quality test and manage power integrity.