As the company was going into is development phase for the Raptor architecture its engineers realized that in FPGAs interconnect takes up more than 80 percent of the resources and also provides lots of room for improvement, according to Frederic Reblewski, CEO and founder of Abound Logic. The company has therefore stayed with a classical SRAM-based look-up table (LUT) based architecture.
In addition the interconnect is transparent to the user meaning that while density can be increased it need not have an impact on EDA software and how Raptor FPGAs are designed.
Reblewski claimed that Abound has been able to create an interconnect architecture with a larger effective fan-out and in which each wire adds an additional effective route. More effective routes for an EDA tool translates into denser logic functionality.
Reblewski claimed the overall effect is that Raptor FPGAs are three times denser than competing architectures. "Memory, DSP, I/0 are not denser but overall is this still translates into 2X, or a process node advantage," he said.
The result is what Reblewski claims is the highest capacity FPGA in 65-nm process node and one that can compete with devices from rivals made on 45-nm to 40-nm silicon. The Raptor has 750k LUTs 38-Mbits of memory, 448 DSP ALUs capable of 24 x 24 bit multiplication, up to 1,200 I/Os) and up to 32 SerDes lanes. The silicon consumes 2.5 watts of static power and can typical yield twice the performance at less power than competing products
Abound Logic, received first silicon from its foundry Taiwan Semiconductor Manufacturing Co. Ltd. in August 2008 and packaged devices in October.
Reblewski said engineering samples are available now and volume shipments would begin in September. As to price, Reblewski said Raptor is "competitive."
Related links and articles: