The ARM models released support 13 processor cores including the ARM926E processor core. The models are instruction accurate, typically enabling simulation speeds of hundreds of MIPS, and in addition to working in OVP virtual platforms, the models include SystemC/TLM-2.0 interfaces, enabling native operation in SystemC environments.
"In the automotive electronics industry we always need to do more testing of our embedded systems software. Finding that the simulation performance of the Imperas/OVP ARM model was over 50 times faster than our previous solution opens up new possibilities for us in software testing, and enables us to increase our test coverage and product reliability," said Urban Forssell, CEO of Nira Dynamics AB (Goteborg, Sweden), a subsidiary of Audi Electronics Venture GmbH, in a statement issued by OVP founder Imperas Ltd. (Thame, England).
"The models of the ARM processor cores give OVP users needed models. Also, working with Synopsys as a founding member of the System-Level Catalyst Program ensures interoperability with the popular Synopsys system-level tools, the DesignWare System-Level Library of models, and virtual platforms using the Innovator development environment," said Simon Davidmann, president and CEO of Imperas and founding director of the OVP initiative.
Gert-Jan Tromp, senior consultant at Dizain-Sync BV (Borne, The Netherlands), said that "We were excited to have achieved over 500 MIPS performance for an ARM7 virtual platform benchmark using OVPsim. We were similarly excited at how easy it was to use OVP processor models in a TLM-2.0 virtual platform."
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