As the compute power of handheld devices approaches that of traditional computers through the use of GHz+ processor cores and increased levels of functionality, the power signature of such devices must be carefully controlled to not only make the products commercially viable, but to make them competitive in the market. As seen in figure 1, if the power density of a handheld device exceeds a narrow band, it will be too hot and must
be re-designed because a human hand will not be able to hold the device for any period of time.
So, in order to be competitive, IC designs that power data centers and mobile handheld devices not only need to control and reduce their overall power consumption, but also must excel in other metrics such as performance per watt or performance per Gbps. As consumers become more aware of the power their electronic systems consume, whether based on environmental concerns, cost sensitivity or application needs, system and component designers must re-think their design goals and methodologies. Depending on the application (server,
networking, 3D graphics, handheld device, etc.), the specific area of power consumption to be addressed for a particular design can be different. For example, in a processor or SoC for a handheld device, very low levels of
operational and standby power targets are critical design criteria.
The need for implementing design and circuit changes in order to achieve successful low power designs is quite apparent, as shown in figure 2. The red curve illustrates the increasing levels of power that a design generates to meet advanced functionality needs (assuming no low power approaches are used), versus the yellow curve that bounds the maximum power consumption allowed in such systems. This disconnect obviously indicates that
comprehensive design, circuit, and process changes must be made to bridge the gap.
Several techniques and methodologies have emerged to target low power design needs, however they do not contribute to reducing the operational or standby power numbers. They either have a marginal impact, or come too late in the design cycle. This approach towards power is usually ad hoc and is superseded by timing, area and routing considerations.
To meet the challenges outlined earlier, a new design methodology that considers power as a design target should be adopted and followed through the entire design chain; starting from the micro-architecture definition and continuing through the RTL design period all the way to physical implementation and sign-off. By employing this process early, you can identify areas of opportunity for power reduction and benefit from the freedom to implement circuit changes that will help in power reduction.
Additionally, power consumed by the chip (at block or full-chip level), should be tracked through the entire design process to ensure convergence on the power goals set for the design. However, to be successful this methodology must go hand-in-hand with other design targets including performance, area, noise and timing. So the design changes proposed by the low power methodology should be simulated and reviewed within the context of these other important design requirements. A comprehensive holistic approach to low power design that analyzes power throughout the entire process; identifying and implementing changes in the circuit that realize power reduction with consideration for other design goals, is a “design for power” methodology.
Using a design for power methodology helps achieve the following:
(a) It ensures that power is considered from the beginning of the design, starting with architectural considerations.
(b) Identifies any circuit changes necessary to achieve or exceed power reduction goals.
(c) Isolates “power bugs” that can cause excessive current draw, but would otherwise pass all other checks (i.e., formal verification, etc.).
(d) Verifies the suggested reduction techniques do not adversely affect other design targets such as area,
timing and noise.
(e) Tracks power throughout the design process; through “power regressions” that help immediately flag any
design changes that may be functionally correct, but that can cause power increases.
Once the power target goals are achieved in the RTL stage, the logic and circuit changes and “power bugs” are identified and addressed, then extensive verification must be done. This will ensure that the low power techniques introduced perform and deliver the expected savings, but also that they do not adversely impact the design. For example, the amount of predicted power savings that can be achieved through clock gating may not be realized due to the introduction of clock buffering (during the synthesis phase), that is needed to meet timing and clock skew constraints.
As apparent in figure 3, the margin available to prevent accidental device turn-on continuously shrinks as designers use much lower supply voltages to reduce the power consumption and heat dissipation. Increased levels of noise in the power and ground networks from circuit changes such as clock and power gating that are used to achieve low power targets, impacts an already reduced margin. Referring back to the example of using clock gating to reduce operation power, increased levels of clock buffering can cause high dynamic voltage drop in the design if the placement of these clock buffers is not done optimally.
Power gating is often used for standby power reduction. However, if the implementation of power gating is not properly done, it can affect the performance and functionality of the design, and waste more power. For example, if the power gate is sized improperly, it can introduce excessive drop through the power gate (when sized smaller than needed), or it can cause excessive leakage in the standby mode (if sized larger than needed). Additionally, if the turn-on sequence of the power gates is not well controlled, it can cause a high “rush-current” in the device that generates noise through coupling in other parts of the chip.
Accurate estimation and prediction of voltage drop in the chip is very important for low power designs. So if the system in which the chip operates is not considered in the simulation through incorporating the package and PCB parasitics, the on-die voltage drop analysis is incomplete. The design, optimization and verification of a low power chip must be done in conjunction with the design and optimization of the package that the chip will
reside in, and the PCB that the packaged chip will go on. This can be achieved by providing accurate models of the package and board to the chip team, and by providing an accurate model of the chip to the package and board team. These models must capture all relevant electrical parameters (e.g. all switching current and parasitic information), and must be silicon validated for accuracy.
So, as you look to reduce operational and/or standby power, re-think your design methodology first. Establish power as a design target, starting from the micro-architecture and RTL design process. By leveraging an analysis driven optimization approach, you can explore different power saving modes and not be restricted to only one methodology. Using RTL based power estimation numbers that are available on-die, you can initiate power grid and package design planning and prototyping. Once RTL optimizations are done and a synthesized
netlist is available, layout based power integrity analyses must be performed at the full-chip level, along with the package and PCB models, to quantify the success of the RTL stage optimizations and ensure that voltage drop in the chip is contained. In parallel, the package/PCB must be optimized considering the impact of the die to ensure the power, thermal and signal integrity of the system.
In conclusion, the successful design and delivery of a low power chip requires a comprehensive design for power methodology that impacts not only the design of the IC but also of the entire system to meet the needs and demands of a power-conscious society.
About the author:
Aveek Sarkar is vice president of product engineering and support at Apache Design Solutions Inc. (San Jose, California.)