Blue Pearl announces release 6.0 of EDA software suite

by K C Krishnadas, TechOnline India - February 17, 2012

It includes enhancements that improve support for SystemVerilog and VHDL, as well as FPGA design

Blue Pearl Software, Inc, a provider of next generation EDA software has announced that it is shipping Release 6.0 of its EDA software, Blue Pearl Software Suite, for Windows and Linux operating systems. It includes enhancements that improve support for SystemVerilog and VHDL, as well as FPGA design.

“Our 6.0 Release improves support for SystemVerilog and VHDL and the FPGA synthesis flow. Designers can now mix and match hardware languages in the same design, with language checking that matches their downstream tools,”  said Shakeel Jeeawoody, Director of Product Marketing at Blue Pearl.

Blue Pearl Software Suite offers comprehensive RTL analysis, clock-domain crossing (CDC) checks, and automatic Synopsys Design Constraints (SDC) generation for FPGA, ASIC and SOC designs. Its visualization and validation technology gives users immediate feedback for validating automatically generated timing constraints.
Release 6.0 features include:

• Multi-language support:  Full language support for SystemVerilog and VHDL, so now designers can mix/match any combination of Verilog, SystemVerilog and VHDL in the same design.

• Longest Path Viewer: Users can now visualize the longest paths of their design using the new longest path viewer.

• Improved FPGA synthesis flow: The improved flow with Synplify Pro enables better handling of SDC constraints

• Improved support for Finite State Machine issues: Improved detection of unreachable states.

• Improved waiver handling: User can now select multiple messages at once to apply waivers

• Improved message viewing in Analysis Report viewer: The text of the currently selected message is displayed in full below the overall report.

• Easier to setup/verify DFT checks: You can now specify initialization patterns, scan chains, and test procedures from the GUI.

• Stricter language checks: The tool now does stricter language checks to match downstream products in the flow.

• Improved support for -f files: Users can now both specify a .f file and use the GUI to specify additional input files.
FPGA designers can learn more by registering at 

Blue Pearl also offers hands-on workshops and software evaluations. 

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