SANTA CLARA, California – Ivo Bolsens, chief technology officer of field programmable gate array vendor Xilinx Inc., sees a future where FPGAs are a fundamental part of the system-on-chip, either merged monolithically with software programmable microprocessor cores or making use of multi-die configurations in three dimensional system-in-packages.
Speaking as a keynoter at the DesignCon conference here, Bolsens laid out the concept of the crossover SoC as something similar to the crossover automobile, which combines the attributes of a sports car, passenger vehicle and a station wagon.
FPGAs are well placed to ride Moore's Law down to finer geometries while achieving affordable prices for low-to-medium volume applications. As the leading edge custom ASICs, with their high development costs become less mainstream Bolsens claimed a crossover SoC could offer the best of FPGA and application-specific standard products.
This would happen two ways; through the tight integration of the CPU and programmable logic and through 3-D system-in-package.
The monolithic integration would be the culmination of a trend that started with FPGAs as an I/O extension of a system processor and will end with a network on chip that joins heterogenous hard processor cores with and soft processors with acceleration units implemented in FPGA fabric. Xilinx has its own FPGA-plus-ARM architecture and products in development.
3-D or not to 3-D, that is the question
"The blending of CPU and programmable logic has the advantages of very high bandwidth and low latency," Bolsens said. He added that a key part of the delivery will be a software model that allows developers to move down from a unified behavioral description while choosing which parts to compile for software and which to synthesis into a hardware design for the fabric. The whole thing should work on top of shared memory system with on-chip buses that support memory coherency.
On the packaging front Bolsens said Xilinx is already using a silicon interposer to deliver two FPGA die in a single package and beat Moore's Law in terms of scaling complexity. "You can have tens of thousands of I/Os between the dies in the SIP," he said emphasizing that the used of a silicon interposer as a backplane provides IC-like energy efficiency.
However, this represents 2.5-D, Bolsens said, and as the technology develops it should be possible to start stacking die, notwithstanding careful design for thermal and mechanical flexing effects. "3-D active-on-active [die stacking] opens up the possibilities of new component types, such as memories with very wide interfaces," he added.
The technologies that will allow this to happen are mostly in place; microbumping, through silicon vias, wafer thinning and so on. What remains is the need for more standardization in terms of on-chip buses, multicore messaging protocols, design models and manufacturing standards and 3-D physical design kits.
But with those in place the new crossover SoCs will enable new business models, Bolsens asserted. He forecasted that some chip vendors could become purveyors of these SoC platforms while others would be the integrators application-specific implementations. Some of today's IP core licensors could become vendors of specialized silicon-proven functions that are available in die form for inclusion in a 3-D SIP.
This may be slightly fantastic but Bolsens concluded that heterogeneous multicore SoCs with FPGA fabric is set to change the IC landscape. The only thing missing are the standards to enable it.