Tilera announces plan for 100-core processors

TechOnline India - October 26, 2009

Tilera Corp. will announced plans for a 100-core embedded processors at the Many-Core Virtual Conference this week where system maker Top Layer networks will discuss its use of Tilera's architecture.

SAN JOSE, Calif. — For Mike Paquette and the engineering team at Top Layer Networks, the many-core world is here today. The company is designing a network intrusion detection system using the 64-core processor from startup Tilera Corp. which Monday (Oct. 26) announces plans for a next-gen, 100-core part.

See video of Tilera CEO Omid Tahernia discussing the implications of the company's 100-core processor announcement.

The two companies are among a handful living at the bleeding edge of an emerging many-core era. Analysts and researchers say it could take years--and require major breakthroughs in parallel programming--before the broad computer and embedded industries can follow them.

The transition to parallel software represents the hardest computer science problem in 50 years, said David Patterson, professor of computer science at the University of California, Berkeley and director of a new parallel computing lab there.

Patterson will describe the issues and present a new method for benchmarking many-core processors in a keynote Wednesday (Oct. 28) at the Many-Core Virtual Conference sponsored by EE Times. Top Layer and Tilera will also talk about their experiences at the online event.

Top Layer has an intrusion detection system that can scour packets at rates up to 4.4 Gbits/second using a set of homegrown ASICs and FPGAs. But that wasn't going to cut it for tomorrow's 10 Gbit/s Ethernet networks.

Rather than re-spin all its ASICs and FPGAs, the company started looking for alternatives from fables startups. Today it has a working prototype of its future system that exercises all 64 cores in of Tilera's current high-end processor.

Paquette said his team liked the fact Tilera taps existing Linux tools for symmetric multiprocessing systems, treating its many-core processor like a multi-CPU server. The approach lets Top Layer give a single core many jobs or spread a single job across many cores.

"The hard part was converting our software from the ASIC and FPGA design, nothing specific to the Tilera software which was quite straightforward," said Paquette.

{pagebreak}Now Tilera has disclosed work on its next generation, leaping to 40nm process technology to create a 100-core part. Compared to its existing chips in 90nm technology, the new devices nearly double in data rate (to 1.5 GHz) and offer as much as four times the performance and twice the power efficiency.

The first-generation parts delivered mixed results in a benchmark study performed by market watchers at BDTI in September.

In the new Tile Gx chips, Tilera is adding more multiple/accumulate units to the cores as well as 75 new instructions, a third of them for single instruction, multiple data work. The chips will support up to 32 Mbytes cache and have optional hardware accelerators for cryptography and packet processing.

Up to two crypto accelerators can be called by any core using library functions to handle a security or compression task. A separate packet-processing accelerator is virtualized so it can be used by multiple tasks at a time.

Engineers are still working on the physical layout of the Gx chips, but Tilera opted to announce them now. "Customers are really digging into our road map so we thought the information would start dribbling out soon," said Anant Agarwal, founder and chief technology officer of Tilera and a professor of electrical engineering at MIT where he has worked on multicore processors.

The news comes at a time when Tilera says it is days away from closing a C round of venture investment for an estimated $24 million.

"We expect this to be our final round and this gets us to break even," said Bob Doud, director of marketing at Tilera. "We're very pleased to be getting funding during this downturn which is a statement in itself," he added.

The company is not disclosing its revenues, but said it has 75 design wins and has shipped several thousand chips since they were announced in 2007. The latest win is in a cloud-computing system being developed by Taiwan's Quanta which makes many of Dell's servers. Quanta recently announced it is investing $10 million in Tilera.

{pagebreak}Other chips and systems are pushing the limits of many-core computing. For example, Cambridge Consultants in England recently talked about its contract design work on 3G and WiMax base stations using devices from PicoChip (Bath, England) that pack 250 cores per chip.

But today the architectures tend to take unique approaches to software. Tilera, for instances, uses a shared memory design so cores can pass data directly, acting like a multiprocessor Linux system.

The Tilera approach requires relatively sophisticated cores, each capable of hosting an operating system. PicoChip, by contrast, uses relatively simpler cores and a message-passing scheme.

Many multicore startups, including Ambric and Cswitch, have tried and failed to establish a wide range of programmable or reconfigurable architectures.

Patterson of Berkeley and other researchers are trying to define easy-to-use parallel programming models that could be employed across a wide variety of poplar chips including X86 processors. He expressed optimism such models can be found, in part due to the broad focus in the industry and academia on creating them.

Berkeley researchers are working across the entire stack from prototyping hardware to new kinds of task schedulers and a handful of killer parallel applications. Indeed, analysts say the lack of applications that can readily be split into many parallel tasks is one of the big barriers for tomorrow's many-core processors.

"There are definitely opportunities for companies such as Top Layer with applications in packet and video processing that are well suited to multicore because they can be broken down into many small calculations," said Linley Gwennap of market watcher The Linley Group (Mountain View, Calif.).

"My skepticism comes in how people take that to the broader $2-3 billion embedded processor market where the apps don't easily get the benefit of scaling the number of cores," he said.

"Everyone is looking for that magic compiler where you hit a button and it makes your code work on a parallel set of cores," added Gwennap. Without such a software panacea "early predictions that multicore would quickly take hold in embedded processors haven't proven to be true," he said.


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