As the size and complexity of modern day SoC’s have increased, it has become imperative to follow a hierarchical approach for which various partitions are created in the design. There are different challenges with the hierarchical approach; especially, while plugging partitions at the chip-top.
One such challenge is Scan Stitching, where a huge design size having partitions can make meeting testability goals challenging. In addition to the challenges faced while stitching different partitions at the top level, there are complications present inside the partitions as well. In this paper we present a case study that covers scan-stitching complications in a hierarchical design at the partition level and also while plugging those partitions at the chip top level.
A pictorial representation of a complex hierarchical design is shown in Figure 1.
Figure 1. Block illustration of a complex hierarchical design
Design had different challenges from a scan stitching perspective:
Challenges at partition level:
1. There were few partitions that had memory inside it, where every memory had soft logic (flip-flops), which was stitched inside the memory but these inbuilt memory chains are needed to be scan stitched with the partition level scan-chains. As memories were large in number it was quite tedious to extract exact number of flip-flops (required for scan chain balancing) and scan information inside the memory using simulations.
2. There was a requirement not to merge internal memory flip-flops with the design flip-flops in a single chain.
Challenges at Chip top level:
1. There were 10 partitions in the SoC and It was required to ensure that the test mode signals are correctly connected at the partition interface.
2. The chain of particular clock domain at the partition level has to be stitched with the same clock domain at the chip top.
In the section below, the challenges at the partition and top level will be discussed in detail.
Challenges at partition level:
Figure 2. Block Level illustration
Figure 2 is a block diagram of a partition. There were mainly two issues faced while doing the scan-stitching at the partition level:
As mentioned earlier, there were memories present inside a few of the partitions, which had internal flip-flops as well. For proper balancing of the chains, it was very important to know the number of already stitched scan-chains inside the memory, number of flops per chain, and corresponding scan-in, scan-out, shift-enable pin and clock domain information as shown in Figure 3.
Figure 3. Memory representation
Considering the large number of memory blocks present in the design, it was not feasible to retrieve all the information manually and use it in design. To resolve above problem, a CTL model of the memories was generated using an ATPG netlist of the memories. These CTL’s are in standard ASCII format that contain all the test related information like test control values, scan chains, shift enables and the clocks defined at the sub-module level. So, all the Test related information was captured in a single file which made scan-stitching flow quite simple and automated.
In general the 2 major sources of power consumption in a design are (i) Clock switching (ii) Memories
Clock switching is maximum in shift mode where clock going to all flip-flops toggle at the same time. In the current design, memories were also included in scan-chains, which worsened the situation. To avoid chip failure due to high power consumption, memory chains were created separately and separate mode of memory bypass was created in the design as shown in Figure 4. This gave Test Engineers an option to bypass the memory in shift mode if the SoC is not meeting the power criteria in test mode.
Figure 4. Memory bypassing logic
Challenges at Chip top level:
After completing the scan-stitching for all partitions, the next challenge was encountered while doing scan-stitching at the chip-top level as shown in Figure 5.
Figure 5. Scan Stitching at the Chip Top
1. The scan ports inside the partition had connectivity internal to the partition only, but connectivity has to be made at the top level as well. To ensure that, CTL model of each partition is also generated and used at the top level stitching (similar to what was done for memory-stitching during scan-stitching of the partition).
2. As already discussed, it was also required to have separate memory scan-chains. The design had memories present inside partition and at top level. To fulfill this requirement, a two step approach was followed:
a) During partition level scan-stitching, a prefix (MEMORY__) was added to the name of chain corresponding to each memory to differentiate memory and normal chains.
b) The above discussed partition level scan-chains acted as a scan-segment while doing scan-stitching at the top level. During top level scan-stitching memory chains were merged with scan-segments having MEMORY__ in their name and normal flops chains were stitched with other scan segments.
3. In addition to above, various test mode connectivity and clock-domain issues at the partition interface were also identified using CTL models of the partitions.
Figure 6. Verifying Test Mode Signal (TMS) connectivity of partition using CTL
As shown in Figure 6, consider a partition (Partition 1) whose TMS pin was supposed to be active high during the scan-stitching at the Partition level. In case it is tied to logic 0, the tool will flag DFT DRC violations at the Chip-Top level while doing scan-stitching. Thus using CTL model the issues at the interface could also be caught.
Considering large number of partitions in a design having many memories, each of which carries internal flops, the CTL based approach helped to streamline the complete scan-stitching flow. As CTL models captures the entire test related information for a partition in a concise form, it really helped in reducing the overall scan-stitching run time and effort.
About the authors:
Goyal works in the physical design team with synthesis as the area of specialization. He has been involved in several block-level and chip-level designs in technology ranging from 90nm to 40nm, and in digital circuit designing for standard cells in several technology nodes (180-nm, 90-nm, 65-nm, 55-nm, 40-nm) for a wide range of processes like Bulk technology, Floating gate and Non-Volatile Memory.
Sachdeva has 6 years of experience in logical and Physical Synthesis, Static Low Power Verification, Formal Verification and has also worked in the EDA industry.
Mahajan has four years of experience in various domains such as logical and physical Synthesis, Static Timing Analysis, Place and Route and static low power verification.