During the last decade, connected devices resulting from cross pollination of Internet and mobile phone technologies dominated the electronics world. Personalized products and services have penetrated our society so much that it is hard to imagine life in their absence. To achieve the desired user experience, these devices are powered with a hardware known as 'system on chip' (SoC). While the semiconductor industry often adheres to Moore's law and doubles the number of transistors in a given area every two years, the onset of application driven designs further adds pressure to support multiple applications in one device i.e. more hardware on the same chip. If 'connectivity' was the buzz for a while, 'intelligent connected solutions' will dominate the electronics world in this decade. This intelligence comes from additional sensors which means more analog on the chip thereby complicating the SoCs further. Pressure from time to market limit the SoC design schedules, leaving minimal margin of error in the whole process. Verification claiming most part of the schedule becomes all the more critical.
A typical SoC design for a consumer electronic device will have blocks that can be broadly classified into processors, DSP cores, peripherals, memory controllers, layered bus architectures and analog components. An optimal SoC verification strategy should address all the challenges that would be encountered during the process of verification. It should include answers to these questions: ''what to verify', 'how to verify' and 'are we done'.
To access the full Design Article by SmartPlay Technologies India Pvt. Ltd (in PDF format), click <a href="http://www.eetindia.co.in/STATIC/PDF/201103/EEIOL_2011MAR15_EDA_TA_01.pdf?SOURCES=DOWNLOAD"target"_new">www.eetindia.co.in/STATIC/PDF/201103/EEIOL_2011MAR15_EDA_TA_01.pdf?SOURCES=DOWNLOAD</a>here.
About the author:
Gaurav Jalan, Manager - Design Verification, SmartPlay Technologies India Pvt. Ltd
Courtesy of EE Times India