Editor’s Note: This article is reproduced from the Fall 2011 Edition of Xcell Journal, with the kind permission of the editor, Make Santarini. Also worth noting is that this article is based on the combination of low-cost FPGAs and ADCs. The point is that in their new 7 series devices, the folks at Xilinx have added “Agile” analog AMS functionality into the FPGAs, which would allow the discrete ADC to be removed from this design (and from the PCB) thereby reducing the BOM.
Designers traditionally build switch-mode DC/DC converters using analog components (bespoke ICs, operational amplifiers, resistors, capacitors and the like) to control the feedback loop and to generate the pulse-width modulation required for switching. When using analog components like these, you must consider a number of factors, taking tolerances, electrical stresses, aging drift, and temperature drift into account to ensure the stability of the design. Now, the availability of affordable low-powered FPGAs coupled with analog-to-digital converters allows the FPGA to replace the traditional analog approach.
DC/DC converters are designed in one of four main topologies: buck (step-down), boost (step-up), inverting (converting a positive input to a negative output), and SEPIC (single-ended primary inductor converter). SEPIC devices maintain a constant output voltage, stepping the input voltage up or down depending upon the circumstances. For this reason, they are a popular choice for battery-based applications.
The basics of controlling a DC/DC converter are the same regardless of whether you implement the control loop using an FPGA or analog techniques. The switch-mode regulator stores energy within an inductor and transfers this energy to the output under the control of the regulation feedback loop, with the chosen topology determining the effect upon the output voltage. This transfer of charge from the inductor to the output is achieved via a switching FET that’s driven by a pulse-width-modulated signal from the controller. The controller uses the difference between the current output voltage and the desired reference voltage to adjust the duty cycle of the PWM to ensure it maintains the desired output voltage during large current transients or during startup of the system.
Table 1. Output voltage relationship to
input voltage and duty cycle (D)
An FPGA-based system requires the same modules as an analog one – namely, PWM generation, error calculation and a control algorithm to adjust the PWM. At the same time, the FPGA delivers a number of distinct advantages, most of them easily achievable within the FPGA itself without any special requirements except for a bit of HDL coding. However, this technique needs an analog-to-digital conversion scheme (either ADC based or some other approach) to feed back the current output voltage into the FPGA, facilitating the control algorithm’s ability to determine the adjustment required to the PWM output.
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