Arasan Chip Systems has announced the availability of its USB 2.0 HSIC PHY IP. The USB 2.0 HSIC (High Speed Inter Chip) Standard is being rapidly adopted by the mobile industry as a means of connecting subsystems within smartphones and tablets. Recently introduced applications processors for these markets, including Texas Instruments’ OMAP5, Marvell’s 600 series and Samsung’s Exynos, all include HSIC interfaces.
USB 2.0 HSIC PHY is a cost effective and lower power replacement for a standard USB 2.0 PHY in applications where USB is being used on a single printed circuit board. It is becoming increasingly attractive to use USB as a high speed chip-to-chip interconnect within a product where low cost and low power are required. However, because USB was designed to enable hot-plugging of peripherals over cables up to 5 meters in length, certain power and implementation features are not required for chip-to-chip interconnect solutions. To better meet the needs of a USB chip-to-chip interconnect, HSIC accomplishes this by removing the analog transceivers, thus reducing complexity, cost and manufacturing risk.
The Arasan USB 2.0 HSIC PHY IP offers:
- Full compliance with USB 2.0
- HSIC specificationProven-in-silicon quality
- High-Speed 480 Mbps data rate
- Full compatibility with UBS Device, Host, Hub and OTG controllers
- GDSII delivery format to simplify integration and timing closure
- Low power consumption (No power consumed unless a transfer is in progress)
- Signals driven at 1.2V standard LVCMOS levels
Arasan’s HSIC interface ships with a complete verification suite designed for rapidintegration in the customer’s SoC test environment. Verification IP is supplied, as well as documented source code, so that it is easy to understand and integrate into the user’s verification environment.
The Arasan USB 2.0 HSIC PHY IP solution, including IP core, Verification IP and documentation is available immediately for licensing.Based in San Jose, CA, USA, Arasan Chip Systems has a 16 year track record of IP and IP standards development leadership.