Altera integrates ARM processor in FPGAs

by Colin Holland , TechOnline India - October 13, 2011

A family of ARM-based SoC FPGAs developed by Altera integrates 28-nm Cyclone V and Arria V FPGA fabric, a single- or dual-core ARM Cortex-A9 MPCore processor

A family of ARM-based SoC FPGAs developed by Altera Corp., integrates 28-nm Cyclone V and Arria V FPGA fabric, a single- or dual-core ARM Cortex-A9 MPCore processor, error correcting code (ECC) protected memory controllers, peripherals and high-bandwidth interconnect into a single chip.

The FPGAs feature a processor system with a 800 MHz ARM Cortex-A9 MPCore processor, NEON media processing engine, single/double-precision floating point unit, L1 and L2 caches, ECC-protected memory controllers, ECC-protected scratchpad memory and a range of used peripherals.

The processor system can deliver 4,000 DMIPS peak performance for less than 1.8 watt with the the processor system and FPGA fabric being powered independently and can be configured and booted in any order. Once in operation, the FPGA portion can be powered down as needed to conserve system power.

The FPGA can be configure using number of methods including serial flash, parallel flash, PCI Express and the hard processor system (HPS) under program control. You can also program the processors to configure other FPGA devices in the system. The processor system can boot from dedicated HPS interfaces, such as Queued Serial Peripheral Interface (QSPI) flash memory and Ethernet, or from user-defined interfaces in the FPGA logic.

The ARM Cortex-A9 MPCore processor system and FPGA are interconnected by high throughput data paths, providing over 125-Gbps peak bandwidth with integrated data coherency.

Based on a low-power 28-nm process (28LP) the devices embedded transceivers  operate up to 5-Gbps for the Cyclone V and 10-Gbps for the and Arria V. The FPGA fabric includes variable-precision DSP blocks and up to three ECC-protected memory controllers.

 

 

The HPS includes a selection of  peripherals including two 10/100/1000 Mbps EMACs which are compliant with the IEEE 802.3-2005 standard, IEEE 1588-2002, and IEEE 1588-2008 standards for precision networked clock synchronization. The controllers also support multiple TCP/IP offload functions. The EMACs have integrated DMA controllers. Two USB OTG controllers support USB 2.0 host and device operation. The USB OTG controller has an integrated DMA controller. A NAND controller supports NAND flash with optional ECC support while the QSPI flash controller supports QSPI serial NOR flash devices.
A DMA controller provides up to eight channels of high-bandwidth data transfer for modules without integrated DMA controllers and ARM CoreSight debug and trace modules facilitate software development and debug, providing interfaces to industry standard debug probes.

A set of low-speed general purpose peripherals is connected to the HPS via a 32- bit Advanced Peripheral Bus (ABP) interconnect and include an interval timer, GPIO, UART, SPI, CAN and I2C.

The FPGA-to-HPS bridges allows logic in the FPGA fabric to master components in the HPS and provide a maximum of 128-bit AMBA AXI interface in both read and write directions at a sped of 245 MHz typical in Arria fabric, 200 MHz typical in Cyclone V fabric while providing asynchronous clock crossing with the clock provided from FPGA logic.

The HPS-to-FPGA bridges allow components in the HPS to master components in the FPGA fabric and provides a maximum of 128-bit AMBA AXI interface in read and write directions at a speed of 245 MHz typical in Arria V fabric, 200 MHz typical in Cyclone V fabric while providing asynchronous clock crossing with the clock provided by FPGA logic and a 32-bit HPS-to-FPGA bridge is dedicated to peripheral control and status register (CSR) accesses.

 

 

 

Altera’s Quartus II software can be used to create custom peripherals and hardware accelerators which can then be integrated them with the processor system using the company's Qsys system integration tool. Qsys speeds hardware design process by automatically generating interconnect logic to connect intellectual propety (IP) functions and subsystems. It automatically generates an FPGA-optimized network-on-a-chip interconnect.

Qsys supports industry-standard interfaces including Avalon Memory-Mapped, Avalon Streaming and AMBA AXITM from ARM, enabling the reuse of IP cores with multiple interfaces in a single design.
The SoC FPGAs are based on the standard ARM Cortex-A9 MPCore processor making them compatible with the existing ARM software ecosystem. Software development for systems based on SoC FPGAs can be done using Altera’s SoC FPGA Virtual Target which is available for purchase now.

SoC FPGA silicon will be available the second half of 2012 followed by reference designs and development boards. Altera’s SoC FPGA pricing starts at less than $15 in high volumes. 

A more detailed pdf providing a product overview of the SoC FPGAs is available here.

 

 

 

 

 

 

 


The Cyclone V SoC FPGAs feature up to 110K logic elements (LEs)  while
the Arria V SoC FPGAs have up to 460K LEs.

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