Forte Design Systems ships latest ASIC and FPGA high-level synthesis

by Clive Maxfield , TechOnline India - June 08, 2011

Forte Design Systems has begun shipping the latest version of its Cynthesizer SystemC high-level synthesis (HLS) software, offering improved performance and quality of results (QoR).

I've just heard from the folks at Forte Design Systems that’s they’ve begun shipping the latest version of their Cynthesizer SystemC high-level synthesis (HLS) software, offering improved performance and quality of results (QoR).

Over the last six months, the Forte R&D team added new features and improved existing features to Cynthesizer, used in more than 300 production application specific integrated circuit (ASIC) and system-on-Chip (SoC) silicon tapeouts since 2002.  Upgrades across the entire tool make it easier to design all aspects of ASICs, SoCs, or field programmable gate arrays (FPGAs) from SystemC.

“High-level synthesis is more than turning C code into RTL,” states Brett Cline, Forte’s vice president of sales and marketing.  “To achieve success, HLS software must have the right abstraction in the input language, a rich feature set that allows the designer to achieve the desired architecture, and great quality of results.  Cynthesizer meets these requirements and sets the direction for the rest of the market segment.”

Cynthesizer’s upgrades and new features

The new version of Cynthesizer adds features required for success in complex real-world chip designs, including an upgraded version of its Interface Generator with the ability to automatically generate interfaces that incorporate clock domain crossing (CDC) circuits.  This allows designs built with Cynthesizer to be used in

multi-clock systems.  The Interface Generator reduces design and verification time by creating pre-validated SystemC source code for complex interfaces, such as line buffers, circular buffers, streaming interfaces and memory interfaces.

New application project templates that define project structure and communication mechanisms include the testbench structure, making it easier for design teams to get started.  Designers can choose from a library of templates based on specific project needs.   Each template comes with transaction level modeling (TLM) and pin-level synthesizable interfaces.

Cynthesizer’s runtime has been improved with the addition of a datapath component cache.  As Cynthesizer processes a design, it uses a  “parts cache” to keep the datapath components created during the HLS process.  During each subsequent execution, Cynthesizer will reuse components, incrementally synthesizing only portions of the design that are needed.   Since the usual development cycle involves synthesizing slightly different versions of a design until the functionality is complete and correct, the use of the cache can reduce overall runtime by as much as 90%.

Many designs include arrays that the designer wants to implement as registers.  The new version of Cynthesizer allows these arrays to be implemented as register banks with multiplexing and access logic customized according to the design requirements.  Use of this feature improves runtime, capacity and ease of use without requiring the user to restructure the algorithm.

Additional runtime improvements have been made through the introduction of advanced scheduling algorithms for pipelined designs along with additional reporting to identify loop-carried dependencies (LCDs) to assist users in optimizing performance of pipelined designs and reducing overall register count.  This allows designers to achieve their design goals more quickly using their existing algorithmic code.

Additionally, Forte recently launched a blog called CynCity to educate visitors to the Forte website on the latest trends and technologies in high-level synthesis.  Current topic topics are complex interfaces and transaction-level modeling (TLM).  The blog, which is located at cyncity.ForteDS.com, covers topics of interest to Cynthesizer users and others who are using or considering high-level synthesis.

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