A virtual target from Altera is based on virtual prototyping solutions from Synopsys Inc.and is aimed at developing device-specific embedded software for Altera’s SoC FPGA devices.
The SoC FPGA virtual target is a PC-based functional simulation of an Altera SoC FPGA development board and is binary- and register-compatible, functional equivalent of the SoC FPGA board.
Linux- and VxWorks-enabled and supported by ARM ecosystem development tools, the virtual target allows use of familiar tools to maximize legacy code reuse.
Provided as a prebuilt, ready-to-use, binary- and register-compatible PC-based simulation model, the SoC FPGA virtual target features the same dual-core ARM Cortex-A9 MPCore processor and system peripherals found in Altera’s Cyclone V and Arria V SoC FPGAs, along with board-level components, including DDR SDRAM, flash memory, and virtual I/Os.
To enable application software development targeting both the hardened processor system and customer-designed FPGA-based IP, Altera will provide an optional FPGA-in-the-loop extension to the virtual target. This extension uses an Altera FPGA development board connected to the PC-based virtual target over a PCIe interface.
The virtual target and the FPGA-in-the-loop extension together let users add custom peripherals and hardware accelerators to the processor subsystem, create device drivers for them, and integrate with application software prior to final hardware availability.
The virtual target comes with initial support for Linux and VxWorks. Embedded software developers can boot Linux using a prebuilt Linux kernel image with device driver support for all the major components of the SoC FPGA development board. Free downloads of a prebuilt GNU tool chain and Linux source also are available from Altera.
A VxWorks board support package (BSP) will be available this quarter for the virtual target, with more BSPs to come for other embedded operating systems.
Supported development tools for the virtual target include the GNU tools, ARM RVDS, the ARM Development Studio 5 (DS-5), the Lauterbach TRACE32 debugger and the Wind River
Workbench. As a simulation model, the virtual target offers more visibility into the system under debug, allows users greater control of the target execution (especially in a multicore system), and performs many debugging tasks that are hard or impossible on hardware.
The SoC FPGA virtual target is available now from Altera with the FPGA-in-the-loop extension planned for early next year.